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1. 发明授权

US08490107B2 Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels 有权
标题翻译：处理支持不同优先级的事务请求的集成电路中的资源分配
公开(公告)号：US08490107B2
公开(公告)日：2013-07-16
申请号：US13137362
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
IPC分类号： G06F9/46 , G06F15/16 , G06F15/173
CPC分类号： H04L47/821 , H04L47/70 , H04L47/805
摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.
摘要翻译：集成电路2包括经由基于环的互连30与共享高速缓存22,24进行通信的多个事务源6,8,10,12,14,16,18,20，每个具有相关联的POC / POS 30,34，以及作为请求维修电路。请求服务电路具有可被分配给不同事务的一组处理资源36。可以动态地或静态地分配这些处理资源。可以根据选择算法进行静态分配。该选择算法可以使用服务质量值/优先级作为其输入变量之一。还可以定义饥饿比例，使得如果饥饿分配太长时间，则强制选择较低的优先级。可以在服务质量值和优先级之间进行可编程映射。分配给每个优先级的处理资源的最大数量也可以被编程。

2. 发明申请

US20130042078A1 Snoop filter and non-inclusive shared cache memory 有权
公开(公告)号：US20130042078A1
公开(公告)日：2013-02-14
申请号：US13137359
申请日：2011-08-08
申请人： Jamshed Jalal , Brett Stanley Feero , Mark David Werkheiser , Michael Alan Filippo
发明人： Jamshed Jalal , Brett Stanley Feero , Mark David Werkheiser , Michael Alan Filippo
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0815 , G06F12/0828 , G06F12/084 , G06F12/0846
摘要： A data processing apparatus 2 includes a plurality of transaction sources 8, 10 each including a local cache memory. A shared cache memory 16 stores cache lines of data together with shared cache tag values. Snoop filter circuitry 14 stores snoop filter tag values tracking which cache lines of data are stored within the local cache memories. When a transaction is received for a target cache line of data, then the snoop filter circuitry 14 compares the target tag value with the snoop filter tag values and the shared cache circuitry 16 compares the target tag value with the shared cache tag values. The shared cache circuitry 16 operates in a default non-inclusive mode. The shared cache memory 16 and the snoop filter 14 accordingly behave non-inclusively in respect of data storage within the shared cache memory 16, but inclusively in respect of tag storage given the combined action of the snoop filter tag values and the shared cache tag values. Tag maintenance operations moving tag values between the snoop filter circuitry 14 and the shared cache memory 16 are performed atomically. The snoop filter circuitry 14 and the shared cache memory 16 compare operations are performed using interlocked parallel pipelines.

3. 发明授权

US08935485B2 Snoop filter and non-inclusive shared cache memory 有权
标题翻译：监听过滤器和非包容性共享缓存
公开(公告)号：US08935485B2
公开(公告)日：2015-01-13
申请号：US13137359
申请日：2011-08-08
申请人： Jamshed Jalal , Brett Stanley Feero , Mark David Werkheiser , Michael Alan Filippo
发明人： Jamshed Jalal , Brett Stanley Feero , Mark David Werkheiser , Michael Alan Filippo
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0815 , G06F12/0828 , G06F12/084 , G06F12/0846
摘要： A data processing apparatus 2 includes a plurality of transaction sources 8, 10 each including a local cache memory. A shared cache memory 16 stores cache lines of data together with shared cache tag values. Snoop filter circuitry 14 stores snoop filter tag values tracking which cache lines of data are stored within the local cache memories. When a transaction is received for a target cache line of data, then the snoop filter circuitry 14 compares the target tag value with the snoop filter tag values and the shared cache circuitry 16 compares the target tag value with the shared cache tag values. The shared cache circuitry 16 operates in a default non-inclusive mode. The shared cache memory 16 and the snoop filter 14 accordingly behave non-inclusively in respect of data storage within the shared cache memory 16, but inclusively in respect of tag storage given the combined action of the snoop filter tag values and the shared cache tag values. Tag maintenance operations moving tag values between the snoop filter circuitry 14 and the shared cache memory 16 are performed atomically. The snoop filter circuitry 14 and the shared cache memory 16 compare operations are performed using interlocked parallel pipelines.
摘要翻译：数据处理装置2包括多个事务源8,10，每个事务源8包括本地高速缓冲存储器。共享高速缓存存储器16将高速缓存行数据与共享高速缓存标签值一起存储。窥探滤波器电路14存储跟踪哪些高速缓存行数据被存储在本地高速缓冲存储器内的窥探滤波器标签值。当针对目标高速缓存行数据接收事务时，监听滤波器电路14将目标标签值与窥探过滤标签值进行比较，共享高速缓存电路16将目标标签值与共享缓存标签值进行比较。共享高速缓存电路16以默认的非包容模式运行。共享高速缓存存储器16和窥探过滤器14相对于共享高速缓冲存储器16内的数据存储而相对地表现为非包容性，而在包含窥探过滤器标签值和共享高速缓存标签值的组合动作的情况下，包含标签存储。在窥探滤波器电路14和共享高速缓冲存储器16之间移动标签值的标签维护操作被原子地执行。窥探滤波器电路14和共享高速缓冲存储器16的比较操作使用互锁的并行流水线进行。

4. 发明授权

US09477600B2 Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode 有权
标题翻译：用于共享高速缓存控制的装置和方法，包括可选择性地以包含或不包含模式操作的高速缓存行
公开(公告)号：US09477600B2
公开(公告)日：2016-10-25
申请号：US13137357
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F2212/502 , G06F2212/601
摘要： A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.
摘要翻译：数据处理系统2包括具有多个本地高速缓存存储器和共享高速缓存存储器18的高速缓存层级。基于每个高速缓存行，存储在共享高速缓存存储器18内的状态数据30,32被用于控制该高速缓存根据高速缓冲存储器系统的非包容性操作或包容性操作来存储和管理数据行。基于指示数据的高速缓存行是唯一的还是非唯一的数据来对窥探事务进行过滤。可以根据请求高速缓存行数据的接收到的事务的事务类型来执行从非包容性操作到包含性操作的切换。

5. 发明申请

US20130042252A1 Processing resource allocation within an integrated circuit 审中-公开
标题翻译：处理集成电路内的资源分配
公开(公告)号：US20130042252A1
公开(公告)日：2013-02-14
申请号：US13137360
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Ramamoorthy Guru Prasadh , Michael Alan Filippo , Phanindra Kumar Mannava
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Ramamoorthy Guru Prasadh , Michael Alan Filippo , Phanindra Kumar Mannava
IPC分类号： G06F9/50
CPC分类号： G06F13/374
摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.
摘要翻译：集成电路2包括经由基于环的互连30与共享高速缓存22,24进行通信的多个事务源6,8,10,12,14,16,18,20，每个具有相关联的POC / POS 30,34，以及作为请求维修电路。请求服务电路具有可被分配给不同事务的一组处理资源36。可以动态地或静态地分配这些处理资源。可以根据选择算法进行静态分配。该选择算法可以使用服务质量值/优先级作为其输入变量之一。还可以定义饥饿比例，使得如果饥饿分配太长时间，则强制选择较低的优先级。可以在服务质量值和优先级之间进行可编程映射。分配给每个优先级的处理资源的最大数量也可以被编程。

6. 发明申请

US20130042249A1 Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels 有权
公开(公告)号：US20130042249A1
公开(公告)日：2013-02-14
申请号：US13137362
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo , Ramamoorthy Guru Prasadh , Phanindra Kumar Mannava
IPC分类号： G06F9/46
CPC分类号： H04L47/821 , H04L47/70 , H04L47/805
摘要： An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

7. 发明申请

US20130042070A1 Shared cache memory control 有权
标题翻译：共享缓存内存控制
公开(公告)号：US20130042070A1
公开(公告)日：2013-02-14
申请号：US13137357
申请日：2011-08-08
申请人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo
发明人： Jamshed Jalal , Mark David Werkheiser , Brett Stanley Feero , Michael Alan Filippo
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F2212/502 , G06F2212/601
摘要： A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.
摘要翻译：数据处理系统2包括具有多个本地高速缓存存储器和共享高速缓存存储器18的高速缓存层级。基于每个高速缓存行，存储在共享高速缓存存储器18内的状态数据30,32被用于控制该高速缓存根据高速缓冲存储器系统的非包容性操作或包容性操作来存储和管理数据行。基于指示数据的高速缓存行是唯一的还是非唯一的数据来对窥探事务进行过滤。可以根据请求高速缓存行数据的接收到的事务的事务类型来执行从非包容性操作到包含性操作的切换。

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