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    • 5. 发明授权
    • Demand-based processor clock frequency switching
    • 基于需求的处理器时钟频率切换
    • US06438697B2
    • 2002-08-20
    • US09818981
    • 2001-03-27
    • Lee Warren Atkinson
    • Lee Warren Atkinson
    • G06F132
    • G06F1/3215G06F1/3203G06F11/3409G06F11/3423G06F12/0802G06F2201/86G06F2201/88G06F2201/885Y02D10/126Y02D10/34
    • A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.
    • 电池供电的计算机系统通过监视与系统的操作相关联的各种事件来确定系统何时未使用。 该系统优选地监视高速缓存读取未命中和写入操作的数量,即,高速缓存命中率,并且当高速缓存命中率上升到高于某一水平时,降低系统时钟频率。 当高速缓存命中率高于一定水平时,可以假设处理器正在执行紧密循环,例如当处理器正在等待一个按键被按下时,可以在不影响系统性能的情况下降低频率。 或者,该装置监视存储器页面未命中,I / O写入周期或其他事件的发生,以确定计算机系统的活动级别。