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1. 发明申请

US20120223439A1 TWO-TRACK CROSS-CONNECT IN DOUBLE-PATTERNED STRUCTURE USING RECTANGULAR VIA 有权
标题翻译：使用矩形横截面的双曲线结构中的双轨交叉连接
公开(公告)号：US20120223439A1
公开(公告)日：2012-09-06
申请号：US13410241
申请日：2012-03-01
申请人： James Walter Blatchford , Scott William Jessen
发明人： James Walter Blatchford , Scott William Jessen
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76838 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.
摘要翻译：可以通过在第一多个平行路径轨道中形成第一互连图案并且在第二多个平行路径轨道中形成第二互连图案来形成集成电路，其中第二多个路线轨道与第一多个平行路线轨道交替的路线。第一互连图案包括第一引线图案，并且第二互连图案包括第二引线图案，使得包含第一引线图案的路径轨道紧邻包含第二引线图案的路径轨迹。金属互连线形成在第一互连图案和第二互连图案中。拉伸交叉连接形成在仅连接第一引线和第二引线的垂直连接电平，例如通孔或接触电平。拉伸交叉连接与其他垂直互连元件同时形成。

2. 发明授权

US07745067B2 Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements 有权
标题翻译：在具有禁止音高要求的技术中进行接触和通孔的放置和路径的方法
公开(公告)号：US07745067B2
公开(公告)日：2010-06-29
申请号：US11191078
申请日：2005-07-28
申请人： James Walter Blatchford , Scott William Jessen
发明人： James Walter Blatchford , Scott William Jessen
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.
摘要翻译：提供是制作掩模布局的方法，由方法制成的集成电路器件，计算机可读介质和用于形成接触孔的掩模。该方法可以包括沿着第一轴图案化第一特征，确定与第一特征相邻的第一组区域，其中第一组区域中的每个区域处于远离第一轴线的第一角度内，并且其中每个区域所述第一组区域中的区域在距离所述第一特征的第一距离内，并且在所述第一组区域中的至少一个中构图第二特征以形成掩模布局，其中所述第一特征和第二个特征是虚拟特征和真实特征之一。

3. 发明授权

US08580675B2 Two-track cross-connect in double-patterned structure using rectangular via 有权
公开(公告)号：US08580675B2
公开(公告)日：2013-11-12
申请号：US13410241
申请日：2012-03-01
申请人： James Walter Blatchford , Scott William Jessen
发明人： James Walter Blatchford , Scott William Jessen
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76838 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

4. 发明授权

US08751977B2 Method for generating ultra-short-run-length dummy poly features 有权
标题翻译：用于产生超短距离虚拟聚焦特征的方法
公开(公告)号：US08751977B2
公开(公告)日：2014-06-10
申请号：US12949336
申请日：2010-11-18
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A dummy feature can be formed within a confined space by specifying an allowable dummy feature length even though the feature length may result in contact between the dummy feature and the live feature. After specifying the dummy feature length, a pattern generation (PG) extract can be performed to pull back the dummy feature away from the live feature by an allowable distance. The PG exact process can result in a shorter dummy feature which has a length which is shorter than can be specified directly by design rules, but which passes rule checking.
摘要翻译：一种用于设计光刻掩模组的方法和装置，其在高级技术节点（例如使用实况特征和虚拟特征）提供期望尺寸的多边形特征。即使特征长度可能导致虚拟特征和实况特征之间的接触，也可以通过指定允许的虚拟特征长度来在密闭空间内形成虚拟特征。在指定虚拟特征长度之后，可以执行图案生成（PG）提取，以将虚拟特征从实况特征远离一个允许的距离。 PG精确过程可以产生更短的虚拟特征，其长度短于可以由设计规则直接指定的长度，但是通过规则检查。

5. 发明授权

US08584053B2 Manufacturability enhancements for gate patterning process using polysilicon sub layer 有权
标题翻译：使用多晶硅子层的栅极图案化工艺的可制造性增强
公开(公告)号：US08584053B2
公开(公告)日：2013-11-12
申请号：US13166738
申请日：2011-06-22
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： H01L27/11803 , H01L21/32139 , H01L27/0207
摘要： A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set.
摘要翻译：一种用于设计包括至少一个掩模的掩模组的方法包括从一组设计规则实现至少一个设计规则。设计规则包括与相邻特征之间的可允许间隔有关的规则，掩模组中由不同掩模定义的特征的重叠以及掩模集合的其它特征。

6. 发明申请

US20120225552A1 TWO-TRACK CROSS-CONNECTS IN DOUBLE-PATTERNED METAL LAYERS USING A FORBIDDEN ZONE 有权
标题翻译：使用防盗区的双层金属层的双轨交叉连接
公开(公告)号：US20120225552A1
公开(公告)日：2012-09-06
申请号：US13410236
申请日：2012-03-01
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/768
CPC分类号： H01L23/528 , G03F7/0035 , G03F7/70466 , H01L21/0274 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.
摘要翻译：通过在并行路径轨道中形成第一互连图案并且在交替的平行路径轨道中形成第二互连图案来形成集成电路。第一互连图案包括平行路径轨道中的第一引线图案，并且第二互连图案包括紧邻的路线轨道中的第二引线图案。第一互连图案包括从第一引线图案延伸到第二引线图案的交叉图案。紧邻交叉图案的路径轨道中的排除区域不具有横跨距离为交叉图案的宽度的2至3倍的横向距离的引线图案。金属互连线形成在第一互连图案和第二互连图案区域中，包括通过交叉图案区域的连续金属交叉线。排除区域不含金属互连线。

7. 发明申请

US20120131522A1 METHOD FOR GENERATING ULTRA-SHORT-RUN-LENGTH DUMMY POLY FEATURES 有权
标题翻译：用于产生超短距离长距离聚合物特征的方法
公开(公告)号：US20120131522A1
公开(公告)日：2012-05-24
申请号：US12949336
申请日：2010-11-18
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A dummy feature can be formed within a confined space by specifying an allowable dummy feature length even though the feature length may result in contact between the dummy feature and the live feature. After specifying the dummy feature length, a pattern generation (PG) extract can be performed to pull back the dummy feature away from the live feature by an allowable distance. The PG exact process can result in a shorter dummy feature which has a length which is shorter than can be specified directly by design rules, but which passes rule checking.
摘要翻译：一种用于设计光刻掩模组的方法和装置，其在高级技术节点（例如使用实况特征和虚拟特征）提供期望尺寸的多边形特征。即使特征长度可能导致虚拟特征和实况特征之间的接触，也可以通过指定允许的虚拟特征长度来在密闭空间内形成虚拟特征。在指定虚拟特征长度之后，可以执行图案生成（PG）提取，以将虚拟特征从实况特征远离一个允许的距离。 PG精确过程可以产生更短的虚拟特征，其长度短于可以由设计规则直接指定的长度，但是通过规则检查。

8. 发明授权

US08176443B2 Layout of printable assist features to aid transistor control 有权
标题翻译：可打印辅助功能的布局，以辅助晶体管控制
公开(公告)号：US08176443B2
公开(公告)日：2012-05-08
申请号：US12131370
申请日：2008-06-02
申请人： Benjamen Michael Rathsack , James Walter Blatchford
发明人： Benjamen Michael Rathsack , James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p1) between any two adjacent gate features. Additionally, the IC design layout can include a printable-gate-assist feature placed adjacent to at least one side of the active region, and placed parallel to and at a second pitch (p2) from one first gate feature of the one or more gate features. In various embodiments, a printable-gate-extension feature can be drawn in the design to extend a second gate feature to match a length with a longer neighboring gate feature of the one or more gate features.
摘要翻译：示例性实施例提供了一种用于布置IC设计和IC设计布局的方法。 IC设计布局可以包括放置在有源区域上的一个或多个栅极特征，包括任意两个相邻栅极特征之间的第一间距（p1）。此外，IC设计布局可以包括邻近有源区域的至少一侧放置的可打印门辅助功能，并且平行于并且以一个或多个栅极的一个第一栅极特征的第二间距（p2）放置特征。在各种实施例中，可以在设计中绘制可印刷门延伸特征以扩展第二栅极特征以将长度与一个或多个栅极特征的较长相邻栅极特征相匹配。

9. 发明授权

US07930656B2 System and method for making photomasks 有权
标题翻译：制作光掩模的系统和方法
公开(公告)号：US07930656B2
公开(公告)日：2011-04-19
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

10. 发明申请

US20090101983A1 Method of Achieving Dense-Pitch Interconnect Patterning in Integrated Circuits 有权
标题翻译：在集成电路中实现密集互连模式的方法
公开(公告)号：US20090101983A1
公开(公告)日：2009-04-23
申请号：US11874501
申请日：2007-10-18
申请人： Steven Lee Prins , James Walter Blatchford
发明人： Steven Lee Prins , James Walter Blatchford
IPC分类号： H01L27/092 , H01L21/8238 , G03F7/00
CPC分类号： G03F7/70091
摘要： Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays.
摘要翻译：集成电路（IC）中的器件制造尽可能小，以最小化IC的尺寸，从而降低每个IC的制造成本。以可用的光刻打印机可能的最小间距形成金属互连线。触点和通孔可能的最小间距大于金属互连线可能的最小间距，从而防止用于触点和通孔的致密直线格栅配置。本发明是一种集成电路和一种制造集成电路的方法，其中使用光刻打印机以尽可能小的间距形成金属互连线。触点和通孔被布置成提供与集成电路所要求的组件和金属互连线的连接，在与包括半致密阵列的接触和通孔的最小间距兼容的配置中。

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