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1. 发明授权

US6110831A Method of mechanical polishing 失效
标题翻译：机械抛光方法
公开(公告)号：US6110831A
公开(公告)日：2000-08-29
申请号：US923316
申请日：1997-09-04
申请人： James Thomas Cargo , Ronald James Alexander Holmes , Ruichen Liu , Alvaro Maury
发明人： James Thomas Cargo , Ronald James Alexander Holmes , Ruichen Liu , Alvaro Maury
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/66 , H01L23/544 , H01L21/465
CPC分类号： B24B37/013 , H01L21/31053 , H01L22/26 , H01L22/34 , H01L2924/0002
摘要： A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, illustratively, having a dopant, dye, etc. termed a "marker layer" is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer is deposited upon the marker layer. The undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated.
摘要翻译：公开了利用化学机械抛光（CMP）制造集成电路的方法。示例性地，具有称为“标记层”的掺杂剂，染料等的介电层形成在其上具有部分制造的集成电路的晶片上。未标记的未染色层沉积在标记层上。对未掺杂或未染色的层进行抛光，并监测废料浆料，直到获得指示信号层曝光的信号。信号分析提供了CMP过程何时终止的指示。

2. 发明授权

US07683360B2 Horizontal chalcogenide element defined by a pad for use in solid-state memories 有权
标题翻译：由用于固态存储器的焊盘限定的水平硫族化物元件
公开(公告)号：US07683360B2
公开(公告)日：2010-03-23
申请号：US11378904
申请日：2006-03-17
申请人： Yi-Chou Chen , Hsiang-Lan Lung , Ruichen Liu
发明人： Yi-Chou Chen , Hsiang-Lan Lung , Ruichen Liu
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2463 , H01L45/1226 , H01L45/144 , H01L45/1691
摘要： A memory cell structure includes a substrate having a bottom electrode at least partially disposed within the substrate; a pad disposed at least partially over the substrate; a phase change element having a chalcogenide material, disposed at least partially over the substrate and adjacent to the pad, the phase change element being adjacent and operatively coupled to the bottom electrode; and a top electrode operatively coupled to the phase change element. Moreover, the pad is formed by a method including depositing a first material layer over the substrate, etching the first material layer to form a pad strip and to expose the bottom electrode, and etching the pad strip to from the pad.
摘要翻译：存储单元结构包括具有至少部分地设置在基板内的底电极的基板; 至少部分地设置在所述基板上的垫; 具有硫族化物材料的相变元件，至少部分地设置在所述衬底上并且与所述焊盘相邻，所述相变元件邻近并且可操作地耦合到所述底部电极; 以及可操作地耦合到相变元件的顶部电极。此外，衬垫通过包括在衬底上沉积第一材料层的方法形成，蚀刻第一材料层以形成焊盘条并暴露底部电极，以及将焊盘条从焊盘蚀刻。

3. 发明授权

US06147407A Article comprising fluorinated amorphous carbon and process for fabricating article 失效
标题翻译：包含氟化无定形碳的制品及其制造方法
公开(公告)号：US06147407A
公开(公告)日：2000-11-14
申请号：US49256
申请日：1998-03-27
申请人： Sungho Jin , Ruichen Liu , Chien-Shing Pai , Wei Zhu
发明人： Sungho Jin , Ruichen Liu , Chien-Shing Pai , Wei Zhu
IPC分类号： C23C14/06 , C23C14/22 , C23C14/34 , H01L21/312 , H01L23/532 , H01L23/48
CPC分类号： C23C14/225 , C23C14/0605 , C23C14/3464 , H01L21/3127 , H01L23/5329 , H01L2924/0002
摘要： The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, and more advantageously 2.1 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.
摘要翻译：本发明提供含有低κ，无氢a-C：F层的装置，其具有良好的粘附性和热稳定性。已经发现，与使用气体源（例如CVD）的方法相比，期望性质的组合可通过相对容易的方法获得。具体地，通过溅射沉积形成a-C：F层，仅使用固体源作为氟和碳，并且在没有任何有意添加的含氢源的情况下。进行溅射使得该层含有20至60at。％氟，并且还有利地使得a-C：F表现出约2.0eV或更大的带隙。通过本发明的方法形成的aC：F层在1MHz和室温下表现出3.0或更小，有利地为2.5或更小，更优选为2.1或更小的介电常数，并且至少热稳定 350℃，有利地450℃，绝对值为约100MPa以下。

4. 发明授权

US5395787A Method of manufacturing shallow junction field effect transistor 失效
标题翻译：浅结场效应晶体管的制造方法
公开(公告)号：US5395787A
公开(公告)日：1995-03-07
申请号：US160701
申请日：1993-12-01
申请人： Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
发明人： Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
IPC分类号： H01L29/78 , H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.
摘要翻译：浅连接n沟道场效应晶体管和p沟道场效应晶体管由单个离子注入形成为保形硅化钨层。虽然磷和硼被注入到相同的硅化物区域中，但磷防止硼向外扩散。

5. 发明授权

US5063422A Devices having shallow junctions 失效
标题翻译：器件具有浅结
公开(公告)号：US5063422A
公开(公告)日：1991-11-05
申请号：US515550
申请日：1990-04-26
申请人： Steven J. Hillenius , Joseph Lebowitz , Ruichen Liu , William T. Lynch
发明人： Steven J. Hillenius , Joseph Lebowitz , Ruichen Liu , William T. Lynch
IPC分类号： H01L21/225 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/36
CPC分类号： H01L29/0847 , H01L21/2257 , H01L21/823814 , H01L27/0921 , H01L29/36 , H01L27/0928
摘要： In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.
摘要翻译：在基于CMOS的集成电路中，更严格的设计规则要求源和漏接点比2500 ANGSTROM浅。通过使用特定的器件配置，可以获得浅结，同时提高了闩锁的阻力，并且保持了其他电特性，例如低漏电流。为了实现这一结果，p沟道器件应该具有小于1.12eV的结反向泄漏电流区域的激活能，其中掺杂剂区域比1200安培浅和单调递减的掺杂剂分布。

6. 发明授权

US07371604B2 Method of forming a contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US07371604B2
公开(公告)日：2008-05-13
申请号：US11545988
申请日：2006-10-10
申请人： Ming Hsiu Lee , Ruichen Liu
发明人： Ming Hsiu Lee , Ruichen Liu
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , H01L21/76885 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16
摘要： Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.
摘要翻译：具有I形状和L形的接触结构以及制造I形和L形接触结构的方法被采用在半导体器件中，并且在某些情况下采用相变非易失性存储器件。通过这些方法产生的I形和L形接触结构表现出相对较小的活性区域。确定接触结构尺寸的方法采用能够创建易于重现的结果的常规半导体沉积和蚀刻处理步骤。

7. 发明授权

US06965522B2 Tunneling diode magnetic junction memory 有权
标题翻译：隧道二极管磁结记忆
公开(公告)号：US06965522B2
公开(公告)日：2005-11-15
申请号：US10802333
申请日：2004-03-17
申请人： Hsiang-Lan Lung , Ruichen Liu
发明人： Hsiang-Lan Lung , Ruichen Liu
IPC分类号： G11C11/14 , G11C11/15
CPC分类号： G11C11/16 , H01L43/08
摘要： A tunneling diode magnetic junction memory that eliminates the need for a separate semiconductor diode is disclosed. The diode is formed by an insulating layer that is located between a free magnetic layer and a pinned magnetic layer. The present invention further discloses a method of reading the contents of a memory cell in a bi-directional manner in order to extend a storage life of the memory cell.
摘要翻译：公开了一种不需要单独的半导体二极管的隧道二极管磁结存储器。二极管由位于自由磁性层和固定磁性层之间的绝缘层形成。本发明还公开了一种以双向方式读取存储单元的内容以延长存储单元的存储寿命的方法。

8. 发明申请

US20050045943A1 [NON-VOLATILE MEMORY CELL AND FABRICATION THEREOF] 有权
标题翻译： [非易失性存储单元及其制造方法]
公开(公告)号：US20050045943A1
公开(公告)日：2005-03-03
申请号：US10604884
申请日：2003-08-25
申请人： Hsiang-Lan Lung , Kuang-Yeu Hsieh , Ruichen Liu , Tai-Bor Wu , Jiun-Yi Tseng
发明人： Hsiang-Lan Lung , Kuang-Yeu Hsieh , Ruichen Liu , Tai-Bor Wu , Jiun-Yi Tseng
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L21/28282 , H01L29/42332 , H01L29/7887
摘要： A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.
摘要翻译：描述非易失性存储单元。非易失性存储单元包括衬底，电荷俘获层，栅极和源极/漏极。电荷捕获层包括绝缘层和其中所含的金属纳米颗粒，其中金属纳米颗粒由相同金属的氧化物的热解离形成。栅极设置在电荷捕获层上，源极/漏极位于栅极旁边的衬底中。

9. 发明授权

US5407859A Field effect transistor with landing pad 失效
标题翻译：场效应晶体管与着陆垫
公开(公告)号：US5407859A
公开(公告)日：1995-04-18
申请号：US159897
申请日：1993-12-01
申请人： Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
发明人： Kuo-Hua Lee , Chun-Ting Liu , Ruichen Liu
IPC分类号： H01L21/336 , H01L21/768 , H01L29/78 , H01L21/44
CPC分类号： H01L29/66575 , H01L21/76895
摘要： A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.
摘要翻译：制造场效应晶体管，其具有使用具有亚光刻间隔的图案化电介质作为蚀刻掩模来图案化的窗口焊盘层。晶体管的理想属性包括小结电容。

10. 发明申请

US20070032012A1 I-shaped and L-shaped contact structures and their fabrication methods 有权
标题翻译： I形和L形接触结构及其制造方法
公开(公告)号：US20070032012A1
公开(公告)日：2007-02-08
申请号：US11545988
申请日：2006-10-10
申请人： Ming Lee , Ruichen Liu
发明人： Ming Lee , Ruichen Liu
IPC分类号： H01L21/8244
CPC分类号： H01L27/2409 , H01L21/76885 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16
摘要： Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.
摘要翻译：具有I形状和L形的接触结构以及制造I形和L形接触结构的方法被采用在半导体器件中，并且在某些情况下采用相变非易失性存储器件。通过这些方法产生的I形和L形接触结构表现出相对较小的活性区域。确定接触结构尺寸的方法采用能够创建易于重现的结果的常规半导体沉积和蚀刻处理步骤。

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