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1. 发明授权

US06493814B2 Reducing resource collisions associated with memory units in a multi-level hierarchy memory system 失效
公开(公告)号：US06493814B2
公开(公告)日：2002-12-10
申请号：US09801610
申请日：2001-03-08
申请人： James Stephen Fields, Jr. , Jody Bern Joyner , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Jody Bern Joyner , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F1200
CPC分类号： G06F12/0811
摘要： A system and method for reducing resource collisions associated with memory units. Resource collisions may be reduced in part by a hash that combines the number N bits in the bank selector field with the number M bits adjacent to a region of correlation, e.g., row selector field, in an address to determine which bank in a memory unit, e.g., cache, may store the information associated with the address.

2. 发明授权

US08214600B2 Data processing system and method for efficient coherency communication utilizing coherency domains 失效
标题翻译：数据处理系统和方法，利用一致性域进行有效的一致性通信
公开(公告)号：US08214600B2
公开(公告)日：2012-07-03
申请号：US11055402
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0831
摘要： In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.
摘要翻译：在包括至少第一和第二相干域的高速缓存相干数据处理系统中，主器件在高速缓存相干数据处理系统内进行第一广播，其被限制在传输范围到第一相干域。主机接收第一个一致性域的响应到该操作的第一次广播。如果响应指示仅在第一个相干域中不能进行操作，则主设备通过在第一和第二相干域中执行操作的第二次广播来增加传输的范围。如果响应指示可以在第一相干域中服务操作，则主机不执行第二广播。

3. 发明授权

US07783841B2 Efficient coherency communication utilizing an IG coherency state 失效
标题翻译：使用IG一致性状态的高效一致性通信
公开(公告)号：US07783841B2
公开(公告)日：2010-08-24
申请号：US11836965
申请日：2007-08-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

4. 发明授权

US07774555B2 Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权
标题翻译：数据处理系统和方法，利用相干域指标进行有效的一致性通信
公开(公告)号：US07774555B2
公开(公告)日：2010-08-10
申请号：US11835259
申请日：2007-08-07
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

5. 发明授权

US08230178B2 Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权
标题翻译：数据处理系统和方法，利用相干域指标进行有效的一致性通信
公开(公告)号：US08230178B2
公开(公告)日：2012-07-24
申请号：US11055483
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

6. 发明授权

US07584329B2 Data processing system and method for efficient communication utilizing an Ig coherency state 失效
标题翻译：数据处理系统和利用Ig一致性状态的高效通信方法
公开(公告)号：US07584329B2
公开(公告)日：2009-09-01
申请号：US11055524
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

7. 发明授权

US07779292B2 Efficient storage of metadata in a system memory 有权
标题翻译：元数据在系统内存中的有效存储
公开(公告)号：US07779292B2
公开(公告)日：2010-08-17
申请号：US11836908
申请日：2007-08-10
申请人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
IPC分类号： G06F11/00 , G06F12/00 , G06C29/00
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

8. 发明授权

US07058767B2 Adaptive memory access speculation 失效
标题翻译：自适应内存访问推测
公开(公告)号：US07058767B2
公开(公告)日：2006-06-06
申请号：US10425400
申请日：2003-04-28
申请人： John Steven Dodson , James Stephen Fields, Jr. , Sanjeev Ghai , Jeffrey Adam Stuecheli
发明人： John Steven Dodson , James Stephen Fields, Jr. , Sanjeev Ghai , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0215
摘要： A method and system for speculatively pre-fetching data from a memory. A memory controller on a data bus “snoops” data requests put on the data bus by a bus control logic. Based on information in the header of the data request, such as transaction type, tag, transaction size, etc., a speculative pre-fetch is made to read data from the memory associated with the memory controller. If the speculative fetch turns out to be correct, then the memory controller makes an assumption that the pre-fetch was too conservative (non-speculative), and a pre-fetch for a next data request is performed at an earlier more speculative time. If the speculative fetch turns out to be incorrect, then the memory controller makes an assumption that the pre-fetch was too speculative (made early), and a pre-fetch for a next data request is performed at a later less speculative time.
摘要翻译：用于从存储器中推测性地预取数据的方法和系统。数据总线上的存储器控制器通过总线控制逻辑“窥探”数据总线上的数据请求。基于诸如事务类型，标签，事务大小等的数据请求的报头中的信息，进行推测性预取以从与存储器控制器相关联的存储器读取数据。如果推测性提取结果是正确的，那么内存控制器假定预取过于保守（非推测性），并且在更早的更多投机时间下执行下一个数据请求的预取。如果推测性提取结果不正确，则存储器控制器假定预取太过于推测（提前），并且在稍后较少的推测时间执行下一个数据请求的预取。

9. 发明授权

US07467323B2 Data processing system and method for efficient storage of metadata in a system memory 失效
标题翻译：用于在系统存储器中有效存储元数据的数据处理系统和方法
公开(公告)号：US07467323B2
公开(公告)日：2008-12-16
申请号：US11055640
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Sanjeev Ghai , Warren Edward Maule , Jeffrey Adam Stuecheli
IPC分类号： G06F11/00 , G06F12/00 , G11C29/00
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

10. 发明授权

US07793048B2 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US07793048B2
公开(公告)日：2010-09-07
申请号：US12207445
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。

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