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    • 2. 发明授权
    • System and method for verification of integrated circuit design
    • 集成电路设计验证的系统和方法
    • US07917873B1
    • 2011-03-29
    • US12029683
    • 2008-02-12
    • William CanfieldKhalil Shalish
    • William CanfieldKhalil Shalish
    • G06F17/50
    • G01R31/318314
    • Embodiments of the methods and systems of the present invention may provide improved methods for the verification of an integrated circuit where a verification project for an integrated circuit may be created by selecting a set of intent units corresponding to the integrated circuit design from a library of intent units and linking these intent units to the integrated circuit design. Specifically, in one embodiment each of these intent units may comprise a corresponding code component and text component such that from the set of intent units selected and configured based on the integrated circuit design a verification plan can be generated from the text components of the corresponding intent units while a testbench can be generated from the code components of the corresponding intent units. This testbench can then be used to generate a model for testing the integrated circuit design.
    • 本发明的方法和系统的实施例可以提供用于验证集成电路的改进方法,其中可以通过从意图库中选择与集成电路设计相对应的一组意图单元来创建用于集成电路的验证项目 并将这些意图单元与集成电路设计联系起来。 具体地,在一个实施例中,这些意图单元中的每一个可以包括对应的代码组件和文本组件,使得从基于集成电路设计选择和配置的意图单元集合可以从相应意图的文本组件生成验证计划 单元,同时可以从相应的意图单元的代码组件生成测试平台。 然后,该测试台可用于生成用于测试集成电路设计的模型。