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    • 1. 发明申请
    • PROCESSOR SAFETY TEST CONTROL SYSTEMS AND METHODS
    • 处理器安全测试控制系统和方法
    • US20120310467A1
    • 2012-12-06
    • US13150646
    • 2011-06-01
    • James Mason FaucettMark H. CostinDavid Dean TarbyAubrey Walter Downs, JR.
    • James Mason FaucettMark H. CostinDavid Dean TarbyAubrey Walter Downs, JR.
    • G01M17/00
    • G06F11/2242B60W10/06B60W10/08G01M17/00G07C5/0808
    • First, second, and third processor modules selectively execute a test having N test states while an ignition system of the vehicle is off. N is an integer greater than one. The N test states each include: the first processor module setting a first output to a first predetermined value for one of the N test states; the second processor module setting a second output to a second predetermined value for the one of the N test states; the third processor module setting a third output to a third predetermined value for the one of the N test states; a predetermined expectation for the one of the N test states; and at least one of the first, second, and third processor modules indicating a fault when a fourth output is different than the predetermined expectation. A control module sets the fourth output based on the first, second, and third outputs.
    • 当车辆的点火系统关闭时,第一,第二和第三处理器模块选择性地执行具有N个测试状态的测试。 N是大于1的整数。 N个测试状态各自包括:第一处理器模块将第一输出设置为N个测试状态之一的第一预定值; 所述第二处理器模块将所述N个测试状态之一的第二输出设置为第二预定值; 所述第三处理器模块将所述N个测试状态之一的第三输出设置为第三预定值; 对N个测试状态之一的预期期望; 并且当第四输出不同于预定期望时,第一,第二和第三处理器模块中的至少一个处理器模块指示故障。 控制模块基于第一,第二和第三输出来设置第四输出。