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1. 发明授权

US5552331A Process for self-aligned source for high density memory 失效
标题翻译：高密度存储器自对准源的处理
公开(公告)号：US5552331A
公开(公告)日：1996-09-03
申请号：US500648
申请日：1995-07-11
申请人： James J. Hsu , Steven W. Longcor
发明人： James J. Hsu , Steven W. Longcor
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11526 , H01L27/11534
摘要： An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decouplng the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.
摘要翻译：公开了一种用于保护半导体器件的栅极边缘和相邻源极区域的改进方法。在这种方法中，沿着一种类型的晶体管的栅极形成间隔物，以在自对准源蚀刻期间保护栅极边缘和相邻源极区。沿着相同的间隔电路的第二类型的晶体管的栅极形成不同宽度的间隔，其可以针对不同的电压要求进行优化。该方法特别适用于与需要维持相对较高电压的周边设备相结合的EPROM，闪存EPROM，EEPROM或其它存储单元的形成。通过将存储单元需求与外围设备要求相结合，可以实现更紧密的门间距和更小的单元大小。

2. 发明授权

US5091324A Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures 失效
标题翻译：在VLSI结构中生产最佳内部，长通道和短路MOS器件的过程
公开(公告)号：US5091324A
公开(公告)日：1992-02-25
申请号：US565384
申请日：1990-08-10
申请人： James J. Hsu , Yowjuang W. Liu
发明人： James J. Hsu , Yowjuang W. Liu
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823807 , Y10S148/082
摘要： Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep implant in P regions where short channel NMOS devices will be constructed to provide punchthrough protection, and optionally providing a deep implant in P regions where intrinsic NMOS devices will be constructed to raise the threshold voltage of such intrinsic devices; then masking P regions of the wafer where intrinsic NMOS devices will be constructed; and implanting the wafer to provide a V.sub.T adjustment to optimize threshold voltages of long channel and short channel NMOS and PMOS devices.

3. 发明授权

US4189926A Turbine-condenser support system 失效
标题翻译：涡轮冷凝器支撑系统
公开(公告)号：US4189926A
公开(公告)日：1980-02-26
申请号：US915690
申请日：1978-06-15
申请人： James J. Hsu
发明人： James J. Hsu
IPC分类号： F01D25/28 , F01K11/02 , F28B9/00 , F01K11/00
CPC分类号： F01K11/02 , F01D25/28
摘要： A subatmospheric pressure condenser has an enclosure within which steam is condensed after exhausting from an associated turbine. The enclosure is flexibly connected to the turbine to permit relative movement therebetween. The condenser also has an outer wall which is flexibly connected to the enclosure to define a vacuum balancing chamber therebetween with the outer wall being structurally connected to the turbine for the purpose of reducing the atmospheric pressure force exerted on the turbine's structure by the turbine. The structural connectors between the outer wall and the turbine intersect the enclosure and provide fluid communication therethrough between the turbine's exhaust port and the vacuum balancing chamber. At the intersection between the structural connectors and the enclosure, sleeves are attached to the enclosure in closely spaced surrounding relationship with each of the structural connectors to minimize liquid intrusion therebetween from the enclosure to the vacuum balancing chamber. Since the outer wall is flexibly connected to the enclosure and the vacuum balancing chamber has little or no water intrusion, the outer wall efficiently transmits atmospheric pressure forces exerted thereon through the structural connectors to the turbine and reduce the load on and thus the required size of the turbine's support structure. The sleeve members which fit about the structural connectors permit relative movement therebetween and extend a predetermined distance from the enclosure to further minimize water leakage into and subsequent accumulation thereof in the vacuum balancing chamber.
摘要翻译：低于大气压的冷凝器具有外壳，在从外壳中抽出相关联的涡轮机之后蒸汽冷凝。外壳柔性地连接到涡轮机，以允许它们之间的相对移动。冷凝器还具有外壁，其柔性地连接到外壳以在其间限定真空平衡室，其外壁结构上连接到涡轮机，以便减小由涡轮机施加在涡轮机结构上的大气压力。外壁和涡轮之间的结构连接件与外壳相交，并在涡轮的排气口和真空平衡室之间提供流体连通。在结构连接器和外壳之间的交叉处，套筒以与每个结构连接件紧密间隔的关系连接到外壳上，以最小化从外壳到真空平衡室之间的液体入侵。由于外壁柔性地连接到外壳，并且真空平衡室几乎没有水侵入，所以外壁通过结构连接器将施加在其上的大气压力有效地传递到涡轮机并且减小了所需的尺寸涡轮机的支撑结构。围绕结构连接件配合的套筒构件允许它们之间的相对移动，并且从外壳延伸预定的距离，以进一步最小化渗漏到其中并随后在真空平衡室中的积聚。

4. 发明授权

US5650964A Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge 失效
标题翻译：在放电期间抑制超短通道充电装置的退化的方法
公开(公告)号：US5650964A
公开(公告)日：1997-07-22
申请号：US486192
申请日：1995-06-07
申请人： Jian Chen , James J. Hsu , Shengwen Luan , Yuan Tang , David Kuan-Yu Liu , Michael A. Van Buskirk
发明人： Jian Chen , James J. Hsu , Shengwen Luan , Yuan Tang , David Kuan-Yu Liu , Michael A. Van Buskirk
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14
摘要： A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.
摘要翻译：一种用于对形成在半导体衬底中的浮栅半导体器件进行放电的工艺，该器件具有第一有源区，第二有源区，电荷保持区和在第一和第二有源区之间的沟道，在第一和第二有源区域之间的电荷保持区域之下的距离处。该方法包括以下步骤：向第一有源区施加约4-8伏特的第一正电压; 向第二活动区域施加约0.5-3伏特范围内的第二电压; 将负8伏范围内的第三电压施加到电荷保持区; 并将衬底耦合到地面。第一有源区可以包括MOSFET的源极或漏极区域，并且第二有源区域可以包括MOSFET的源极区域或漏极区域。在另一方面，一种浮动栅极晶体管阵列，每个晶体管包括源极，漏极，栅极和浮置栅极，每个浮置栅极包括电荷; 并且公开了耦合到晶体管的控制逻辑，用于选择性寻址晶体管。在该装置中，为了排出阵列中每个晶体管的浮置栅极：每个源极共同耦合到第一电压; 每个漏极共同耦合到低于第一电压的第二电压; 衬底耦合到地面; 并且每个浮动栅极耦合到负电压。

5. 发明授权

US5013675A Method of forming and removing polysilicon lightly doped drain spacers 失效
标题翻译：形成和去除多晶硅轻掺杂漏极间隔物的方法
公开(公告)号：US5013675A
公开(公告)日：1991-05-07
申请号：US355634
申请日：1989-05-23
申请人： Lewis Shen , Zahra Hadjizadeh-Amini , Hsingya A. Wang , James J. Hsu
发明人： Lewis Shen , Zahra Hadjizadeh-Amini , Hsingya A. Wang , James J. Hsu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/7833
摘要： A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer. The POCl.sub.3 doping of the polysilicon layer increases the etch rate of the polysilicon, thus enhancing the selectivity of the etching of the polysilicon versus the oxide layer.

6. 发明授权

US5553018A Nonvolatile memory cell formed using self aligned source implant 失效
标题翻译：使用自对准源植入物形成的非易失性存储单元
公开(公告)号：US5553018A
公开(公告)日：1996-09-03
申请号：US484580
申请日：1995-06-07
申请人： Hsingya A. Wang , James J. Hsu
发明人： Hsingya A. Wang , James J. Hsu
IPC分类号： H01L21/8247 , H01L29/68
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.
摘要翻译：诸如闪存EEPROM的存储器件采用高能量注入来形成公共源极线，避免了自对准源蚀刻工艺的需要。使用高能量注入和避免蚀刻工艺提供更大的电池均匀性和更好的VT分布。

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