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    • 8. 发明授权
    • Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
    • 通用RSDS-LVDS-miniLVDS-BLVDS差分信号接口电路
    • US06992508B2
    • 2006-01-31
    • US10877543
    • 2004-06-25
    • James Chow
    • James Chow
    • H03K19/094
    • H03K19/018585H04L25/0272H04L25/028H04M3/42017
    • An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.
    • 电子电路包括可选择地配置的差分信号接口和选择控制输入,用于选择多个标准差分信号接口中的一个以配置差分信号接口。 选择控制输入选择以下多个标准差分信号接口之一:减速摆幅差分信号(RSDS),低电压差分信号(LVDS),迷你低电压差分信号(mini-LVDS)和总线低电压差分信号( BLVDS),用于配置差分信号接口。 电子电路还可以包括多个可选择的电压源(611,612,613)和多个可选择的电流源(614,615,616,617),用于响应于选择控制输入端处的输入信号而选择 ,用于差分信号接口的操作DC电压,标准差分信号电压和标准差分信号电流中的至少一个。
    • 9. 发明申请
    • Precision closed loop delay line for wide frequency data recovery
    • 精密闭环延迟线用于宽频数据恢复
    • US20050017774A1
    • 2005-01-27
    • US10921242
    • 2004-08-18
    • James ChowKenny Wen
    • James ChowKenny Wen
    • H03H7/30H03L7/07H03L7/081H03B1/00
    • H03L7/0805H03L7/07H03L7/0812
    • A closed loop delay line system (700) includes a phase lock loop that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input (727) adjusts the speed of the delay line (702). A phase detector (720) compares phase between a first timing signal input (704) and the delay line output (706). A bias adjust circuit (726) mixes the phase compare output signal (725) and the phase lock output signal (715) to provide a combination bias signal (727) to the delay line (702). Additionally, the relative timing position of strobe outputs (734) from the delay line (702) can be individually adjusted.
    • 闭环延迟线系统(700)包括提供锁相输出信号(715)的锁相环。 延迟线(702)包括时钟输入,延迟线输出和延迟线偏置输入。 提供给延迟线偏置输入(727)的偏置信号调整延迟线(702)的速度。 相位检测器(720)比较第一定时信号输入(704)和延迟线输出(706)之间的相位。 偏置调整电路(726)将相位比较输出信号(725)和锁相输出信号(715)混合,以向延迟线(702)提供组合偏置信号(727)。 此外,可以单独调整来自延迟线(702)的选通输出(734)的相对定时位置。