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1. 发明申请

US20060106911A1 Concurrent PCI express with sDVO 审中-公开
标题翻译：并发PCI Express与sDVO
公开(公告)号：US20060106911A1
公开(公告)日：2006-05-18
申请号：US10976488
申请日：2004-10-29
申请人： James Chapple , Sylvia Downing , Scott Janus , Katen Shah , Patrick Smith
发明人： James Chapple , Sylvia Downing , Scott Janus , Katen Shah , Patrick Smith
IPC分类号： G06F15/16
CPC分类号： G06F13/385
摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises transmitting Peripheral Component Interconnect (PCI) Express protocol data on a first set of one or more lanes of a link and concurrently transmitting non-PCI Express protocol data on a second set of one or more lanes of the link.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括在链路的一个或多个车道的第一组上传输外围组件互连（PCI）Express协议数据，并且在链路的一个或多个车道的第二组上同时发送非PCI Express协议数据。

2. 发明申请

US20050289271A1 Circuitry to selectively produce MSI signals 审中-公开
标题翻译：电路选择性地产生MSI信号
公开(公告)号：US20050289271A1
公开(公告)日：2005-12-29
申请号：US10881076
申请日：2004-06-29
申请人： Alberto Martinez , James Chapple , Prashant Sethi , Joseph Bennett
发明人： Alberto Martinez , James Chapple , Prashant Sethi , Joseph Bennett
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In some embodiments, the inventions include a chip having a status register circuit coupled to conductors to receive interrupt event signals to provide source signals corresponding to the interrupt event signals. The chip also includes a control register circuit to provide source enable signals for selective ones of the interrupt sources, and a re-arming logic circuit coupled to the conductors to receive the interrupt event signals and provide a re-arming signal. The chip further includes first logic circuit to receive the source signals, the source enable signals, and the re-arming signal to provide an initial interrupt signal, and message signaled interrupt (MSI) signal pulse generation logic to receive the initial interrupt signal and provide an MSI signal in response thereto. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括具有状态寄存器电路的芯片，其耦合到导体以接收中断事件信号，以提供对应于中断事件信号的源信号。该芯片还包括控制寄存器电路，用于为选择性的中断源提供源使能信号，以及耦合到导体的重新布线逻辑电路以接收中断事件信号并提供重新布防信号。该芯片还包括接收源信号的第一逻辑电路，源使能信号和重新布防信号以提供初始中断信号，以及消息信号中断（MSI）信号脉冲产生逻辑以接收初始中断信号并提供响应于此的MSI信号。描述和要求保护其他实施例。

3. 发明授权

US07971190B2 Machine learning performance analysis tool 有权
标题翻译：机器学习性能分析工具
公开(公告)号：US07971190B2
公开(公告)日：2011-06-28
申请号：US11606553
申请日：2006-11-30
申请人： Bob Davies , James Chapple , William K. Cheung , Guoping Wen , Carolyn Dase , Dan Nowlin
发明人： Bob Davies , James Chapple , William K. Cheung , Guoping Wen , Carolyn Dase , Dan Nowlin
IPC分类号： G06F9/44 , G06F11/30 , G06F15/18
CPC分类号： G06F11/3466
摘要： In general, in one aspect, the disclosure describes a method that includes interrupting a program running on a processor. The active instruction that was interrupted is identified. Event counts since a previous interrupt are harvested.
摘要翻译：通常，在一个方面，本公开描述了一种方法，其包括中断在处理器上运行的程序。确定中断的活动指令。收到以前的中断后的事件计数。

4. 发明申请

US20080133900A1 Machine learning performance analysis tool 有权
标题翻译：机器学习性能分析工具
公开(公告)号：US20080133900A1
公开(公告)日：2008-06-05
申请号：US11606553
申请日：2006-11-30
申请人： Bob Davies , James Chapple , William K. Cheung , Guoping Wen , Carolyn Dase , Dan Nowlin
发明人： Bob Davies , James Chapple , William K. Cheung , Guoping Wen , Carolyn Dase , Dan Nowlin
IPC分类号： G06F9/38
CPC分类号： G06F11/3466
摘要： In general, in one aspect, the disclosure describes a method that includes interrupting a program running on a processor. The active instruction that was interrupted is identified. Event counts since a previous interrupt are harvested.
摘要翻译：通常，在一个方面，本公开描述了一种方法，其包括中断在处理器上运行的程序。确定中断的活动指令。收到以前的中断后的事件计数。

5. 发明申请

US20050243096A1 Memory controller hub interface 有权
标题翻译：内存控制器集线器接口
公开(公告)号：US20050243096A1
公开(公告)日：2005-11-03
申请号：US11174662
申请日：2005-07-06
申请人： Brian Possley , David Puffer , Kurt Robinson , Ray Askew , James Chapple , Thomas Dever
发明人： Brian Possley , David Puffer , Kurt Robinson , Ray Askew , James Chapple , Thomas Dever
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F3/14 , G06T1/20 , G09G5/001
摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译：存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。

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