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1. 发明申请

US20140181484A1 MECHANISM TO PROVIDE HIGH PERFORMANCE AND FAIRNESS IN A MULTI-THREADING COMPUTER SYSTEM 审中-公开
标题翻译：在多线程计算机系统中提供高性能和公平性的机制
公开(公告)号：US20140181484A1
公开(公告)日：2014-06-26
申请号：US13725934
申请日：2012-12-21
申请人： James Callister , Don Soltis , Rohit Bhatia , Ramkumar Srinivasan , Steven Bostian , Richard M. Blumberg
发明人： James Callister , Don Soltis , Rohit Bhatia , Ramkumar Srinivasan , Steven Bostian , Richard M. Blumberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/4881
摘要： According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.
摘要翻译：根据一个实施例，处理器包括用于执行包括第一线程和第二线程的多个线程的执行流水线。处理器还包括耦合到执行流水线的多线程控制器（MTC），以基于从线程切换策略列表中选择的线程切换策略来确定是否在第一和第二线程之间切换线程，所述线程切换策略基于线程切换策略的列表，第一线程和第二线程，并且响应于确定切换线程，从执行第一线程切换到执行第二线程。

2. 发明授权

US6041092A Digital circuit to count like signals in a data word 有权
标题翻译：数字电路像数据字中的信号一样计数
公开(公告)号：US6041092A
公开(公告)日：2000-03-21
申请号：US183311
申请日：1998-10-30
申请人： Li C. Tsai , Richard M. Blumberg
发明人： Li C. Tsai , Richard M. Blumberg
IPC分类号： G06F7/60 , H03M7/22 , G06M3/00
CPC分类号： H03M7/22 , G06F7/607
摘要： A digital circuit for counting the number of zeroes or ones in a data word comprising a plurality of series paths leading to one-hot encoded outputs. Each one-hot encoded output indicates a different number of like signals in the input data word. One of the plurality of series paths is activated by connecting the series path from an input power rail to the one-hot output. A series path is connected through a plurality of transfer gates, each controlled by either a single bit of the input data word or its complement. The series paths may be optimized to share transfer gates by interconnecting them in a tree or lattice structure. Subsections of the input data word may be counted separately in independent tree or lattice structures, then combined in subsequent combinational stages of the circuit. The resulting one-hot encoded count of like signals may then be binary encoded by a final stage of the counting circuit.
摘要翻译：一种数字电路，用于对包含导致一热编码输出的多个串行路径的数据字中的零个数进行计数。每个热编码的输出表示输入数据字中不同数量的类似信号。通过将串联路径从输入电力轨连接到单热输出来激活多个串联路径中的一个。串联路径通过多个传输门连接，每个传输门由输入数据字或其补码的单个位控制。可以优化串联路径以通过将它们以树形或格子结构相互连接来共享传输门。输入数据字的子部分可以在独立的树形或晶格结构中单独计数，然后组合在电路的后续组合阶段。所得到的同样信号的单热编码计数可以由计数电路的最后一级进行二进制编码。

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