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1. 发明授权

US07797258B1 Graphics system transposer read scheduler 有权
标题翻译：图形系统转换器读调度器
公开(公告)号：US07797258B1
公开(公告)日：2010-09-14
申请号：US11556141
申请日：2006-11-02
申请人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
发明人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00 , G06T1/00 , G06T15/00
CPC分类号： G06T1/20
摘要： A graphics system includes a transposer. A read scheduler utilizes a minimum cost analysis to schedule a read transfer order for the transposer to minimize the total number of passes required to process a set of input vectors.
摘要翻译：图形系统包括一个转换器。读调度器利用最小成本分析来调度转移器的读传输顺序，以最小化处理一组输入向量所需的总次数。

2. 发明授权

US07796137B1 Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories 有权
标题翻译：增强的基于标签的结构，用于在高速缓冲存储器中实现独立变量池的系统和方法
公开(公告)号：US07796137B1
公开(公告)日：2010-09-14
申请号：US11552415
申请日：2006-10-24
申请人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
发明人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
IPC分类号： G09G5/36 , G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864
摘要： Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.
摘要翻译：公开了一种装置，系统，方法，图形处理单元（GPU），计算机设备和计算机介质，以实现独立增强标签池，以便除其他之外，分离标签和高速缓存行之间的依赖关系。在一个实施例中，增强的基于标签的高速缓存结构包括被配置为维护增强标签池的标签库。每个增强标签可以具有匹配部分，其被配置为在增强标签和传入地址之间形成关联。此外，增强标签可以具有配置为响应于关联的形成而在高速缓存中定位高速缓存行的数据定位器部分。数据定位器部分使增强标签能够定位多个高速缓存线。有利地，可以形成增强的基于标签的高速缓存结构，以独立于高速缓存线库的延迟容忍度来调整增强标签的可重用性的程度。

3. 发明授权

US07701459B1 Primitive oriented assembly for parallel vertex/geometry processing 有权
标题翻译：平行顶点/几何处理的原始定向装配
公开(公告)号：US07701459B1
公开(公告)日：2010-04-20
申请号：US11556525
申请日：2006-11-03
申请人： Dane T. Mrazek , James C. Bowman , Sameer M. Gauria
发明人： Dane T. Mrazek , James C. Bowman , Sameer M. Gauria
IPC分类号： G06F15/80 , G06T17/00 , G06F13/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.
摘要翻译：图形系统具有不共享顶点信息的并行处理单元。图形系统为并行处理单元构建独立的工作批次，其中每批工作都具有一组基元的顶点列表。

4. 发明授权

US08237725B1 Vertex cache map mode for per-vertex state changes 有权
标题翻译：顶点状态改变的顶点缓存映射模式
公开(公告)号：US08237725B1
公开(公告)日：2012-08-07
申请号：US11935239
申请日：2007-11-05
申请人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
发明人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
IPC分类号： G09G5/36
CPC分类号： G06T15/005 , G06T2210/52
摘要： A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.
摘要翻译：图形处理器中的顶点高速缓存被配置为当不使用每顶点状态改变时作为常规循环流缓存操作，并且当使用每顶点状态改变时被配置为作为随机存取存储缓冲器操作。定义基元和状态变化的顶点批次将输出到并行处理单元，以根据顶点着色器程序进行处理。除了允许每顶点状态改变之外，顶点缓存被配置为存储使用锚点的原始拓扑的顶点，例如三角形条，线环和多边形。

5. 发明授权

US07755631B1 Transposition structures and methods to accommodate parallel processing in a graphics processing unit (“GPU”) 有权
标题翻译：用于在图形处理单元（“GPU”）中适应并行处理的转置结构和方法
公开(公告)号：US07755631B1
公开(公告)日：2010-07-13
申请号：US11552350
申请日：2006-10-24
申请人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
发明人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
IPC分类号： G06F15/00
CPC分类号： G06T1/00
摘要： Disclosed are an apparatus, a method, a programmable graphics processing unit (“GPU”), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e.g., executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.
摘要翻译：公开了一种装置，方法，可编程图形处理单元（“GPU”），计算机设备和计算机介质，以便促进并行数据流的产生，以在至少一部分 GPU的图形流水线。在一个实施例中，设备的输入接收图形元素的数据流中的图形元素。图形管线可以使用图形元素来形成计算机生成的图像。该装置还可以包括被配置为产生并行属性流的转置器。每个并行属性流包括图形元素共有的属性类型。在一个实施例中，转置器可以被配置为将图形流水线的至少一部分从单个数据流转换为多个数据流（例如，由多个执行线程执行），同时减少了实现这种转换的存储器大小要求。

6. 发明授权

US07647467B1 Tuning DRAM I/O parameters on the fly 有权
标题翻译：即时调整DRAM I / O参数
公开(公告)号：US07647467B1
公开(公告)日：2010-01-12
申请号：US11642368
申请日：2006-12-19
申请人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
发明人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.
摘要翻译：在用于存储器（例如，诸如DRAM的高速存储器）和请求访问存储器的处理器之间的接口中使用的参数的飞行调谐。在操作模式中，存储器控制器将处理器耦合到存储器。存储器控制器还可以禁止操作模式启动训练模式。在训练模式下，存储器控制器调节在即将到来的操作模式中使用的一个或多个参数（电压参考，时序偏移等）。对存储器的访问可以来自在图形处理器上运行的同步进程。存储器控制器确定在进入训练模式之前是否可以禁止同步过程。如果同步过程的存储器缓冲器使得训练模式不会影响同步过程，则存储器控制器可以进入训练模式以调整接口参数而不会不利地影响该过程。

7. 发明授权

US07571281B1 Look-up filter structures, systems and methods for filtering accesses to a pool of tags for cache memories 有权
标题翻译：查找过滤器结构，用于过滤对缓存存储器的标签池的访问的系统和方法
公开(公告)号：US07571281B1
公开(公告)日：2009-08-04
申请号：US11445658
申请日：2006-06-02
申请人： Sameer M. Gauria
发明人： Sameer M. Gauria
IPC分类号： G06F13/00
CPC分类号： G06F12/0895
摘要： In one embodiment, an apparatus includes an input port to receive a request to determine whether data units are stored in the cache, as well as an output port to generate look-ups for the pool of tags. The apparatus also includes a look-up filter coupled to the input and output ports, and operates to filter out superfluous look-ups for the data units, thereby forming filtered look-ups. Advantageously, the look-up filter can filter out superfluous look-ups to at least reduce the quantity of look-up operations associated with the request, thereby reducing stalling associated with multiple look-up operations. In a specific embodiment, the look-up filter can include a data unit grouping detector and a look-up suppressor.
摘要翻译：在一个实施例中，装置包括用于接收确定数据单元是否存储在高速缓存中的请求的输入端口以及用于生成标签池的查找的输出端口。该装置还包括耦合到输入和输出端口的查找滤波器，并且用于滤除数据单元的多余查找，从而形成滤波的查找。有利地，查找过滤器可以过滤掉多余的查找，以至少减少与请求相关联的查找操作的数量，从而减少与多个查找操作相关联的停顿。在具体实施例中，查找过滤器可以包括数据单元分组检测器和查找抑制器。

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