专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5465373A Method and system for single cycle dispatch of multiple instructions in a superscalar processor system 失效
标题翻译：用于超标量处理器系统中多个指令的单周期调度的方法和系统
公开(公告)号：US5465373A
公开(公告)日：1995-11-07
申请号：US1864
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
发明人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

2. 发明授权

US07680124B2 Frame mapping scheduler for scheduling data blocks using a mapping table and a weight table 失效
标题翻译：帧映射调度器，用于使用映射表和权重表来调度数据块
公开(公告)号：US07680124B2
公开(公告)日：2010-03-16
申请号：US10903954
申请日：2004-07-30
申请人： Jinhui Li , Ali A. Poursepanj , Mark Benjamin Simkins
发明人： Jinhui Li , Ali A. Poursepanj , Mark Benjamin Simkins
IPC分类号： H04L12/28
CPC分类号： H04L41/0896 , H04L43/026
摘要： A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a weight table and a mapping table. The weight table comprises a plurality of entries, with each of the entries identifying a particular one of the transmission elements. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and an entry of the weight table. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table.
摘要翻译：通信系统的网络处理器或其他处理设备包括调度电路，其被配置为调度用于在帧的时隙中从多个用户或其他传输元件传输的数据块。调度电路利用权重表和映射表。权重表包括多个条目，其中每个条目标识特定的一个传输元件。映射表包括指定帧的特定时隙与权重表的条目之间的映射的至少一个条目。调度电路通过访问对应的映射表条目并利用结果值来访问权重表来确定在给定时隙中要调度的特定传输元件。

3. 发明授权

US07801164B2 Two dimensional timeout table mechanism with optimized delay characteristics 有权
标题翻译：具有优化延迟特性的二维超时表机制
公开(公告)号：US07801164B2
公开(公告)日：2010-09-21
申请号：US11412917
申请日：2006-04-27
申请人： Christopher Koob , Ali A. Poursepanj , David P. Sonnier
发明人： Christopher Koob , Ali A. Poursepanj , David P. Sonnier
IPC分类号： H04L12/56
CPC分类号： H04L1/1883
摘要： Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.
摘要翻译：公开了改进的超时表机制。作为示例，用于在处理系统中为数据队列提供超时延迟的方法包括以下步骤。保持超时结构。超时结构包括两个或更多个组，每个组包括两个或更多个分组，每个分组具有与其相关联的超时延迟值的范围，每个组具有与之相关联的权重，每个组的权重基于速率和数量可分配给每个组的队列。选择要分配给处理系统中的数据队列的超时延迟值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式