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    • 3. 发明授权
    • Row decoder circuit
    • 行解码电路
    • US08493813B2
    • 2013-07-23
    • US13238816
    • 2011-09-21
    • Seung-Won Lee
    • Seung-Won Lee
    • G11C8/08
    • G11C8/10G11C8/08G11C16/08
    • A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals.
    • 行解码器电路包括解码单元和第一和第二字线驱动单元。 解码单元基于选择信号和字线电压产生第一驱动信号和第二驱动信号。 第一驱动信号的电压电平和第二驱动信号的电压电平取决于操作模式。 第一字线驱动单元连接到第一字线,并且基于第一驱动控制信号,将第一驱动信号和第二驱动信号之一作为第一字线驱动信号输出。 第二字线驱动单元连接到第二字线,并且基于第二驱动控制信号输出第一驱动信号和第二驱动信号中的一个作为第二字线驱动信号。
    • 6. 发明授权
    • Internal voltage controllers including multiple comparators and related smart cards and methods
    • 内部电压控制器包括多个比较器和相关的智能卡和方法
    • US07750611B2
    • 2010-07-06
    • US11951594
    • 2007-12-06
    • Seung-Won Lee
    • Seung-Won Lee
    • G05F1/563G05F1/565
    • G05F1/56
    • A voltage controller may include a pulse generator and an internal voltage control circuit coupled to the pulse generator. The pulse generator may be configured to generate a control signal in response to at least one of a mode signal and/or an external voltage. The internal voltage control circuit may be configured to generate an internal voltage at an internal voltage node, and the internal voltage control circuit may include a voltage divider, first and second comparators, and a driver. The voltage divider may be coupled between the internal voltage node and a first reference voltage, and the voltage divider may generate a feedback voltage that is between the internal voltage and the first reference voltage. The first comparator may be configured to generate a first comparison result responsive to comparing the feedback voltage with a second reference voltage, and the second comparator may be configured to generate a second comparison result responsive to comparing the feedback voltage with the second reference voltage in response to the control signal. The driver may be coupled between an external voltage and the internal voltage node, and the driver may be configured to generate the internal voltage responsive to the first and second comparison results. Related methods and smart cards are also discussed.
    • 电压控制器可以包括脉冲发生器和耦合到脉冲发生器的内部电压控制电路。 脉冲发生器可以被配置为响应于模式信号和/或外部电压中的至少一个而产生控制信号。 内部电压控制电路可以被配置为在内部电压节点处产生内部电压,并且内部电压控制电路可以包括分压器,第一和第二比较器以及驱动器。 分压器可以耦合在内部电压节点和第一参考电压之间,并且分压器可以产生处于内部电压和第一参考电压之间的反馈电压。 第一比较器可以被配置为响应于将反馈电压与第二参考电压进行比较而产生第一比较结果,并且第二比较器可以被配置为响应于响应于将反馈电压与响应于第二参考电压进行比较而产生第二比较结果 到控制信号。 驱动器可以耦合在外部电压和内部电压节点之间,并且驱动器可以被配置为响应于第一和第二比较结果而产生内部电压。 还讨论了相关方法和智能卡。
    • 8. 发明申请
    • Semiconductor device and method for compensating voltage drop of a bit line
    • 用于补偿位线电压降的半导体器件和方法
    • US20070285990A1
    • 2007-12-13
    • US11648293
    • 2006-12-29
    • Seung-Won Lee
    • Seung-Won Lee
    • G11C11/34
    • G11C16/26G11C7/12G11C7/14G11C16/24
    • Provided are a semiconductor device and a method for compensating for a voltage drop of a bit line. The semiconductor device includes at least one monitoring bit line and at least one main memory bit line, and monitors a voltage of the at least one monitoring bit line after a precharging operation and supplies a predetermined compensation current to the at least one monitoring bit line and the at least one main memory bit line based on a monitoring result. Accordingly, it is possible to precisely compensate for a voltage drop occurring in the main memory bit line due to under precharge or leakage current, thereby preventing unnecessary compensation current from being supplied. Therefore, it is possible to stably perform a read operation of the semiconductor device.
    • 提供一种用于补偿位线的电压降的半导体器件和方法。 所述半导体器件包括至少一个监视位线和至少一个主存储器位线,并且在预充电操作之后监视所述至少一个监视位线的电压,并将预定补偿电流提供给所述至少一个监视位线;以及 所述至少一个主存储器位线基于监视结果。 因此,可以精确地补偿由于在预充电或漏电流之下在主存储器位线中发生的电压降,从而防止不必要的补偿电流被提供。 因此,可以稳定地执行半导体器件的读取操作。
    • 9. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US07016232B2
    • 2006-03-21
    • US10922122
    • 2004-08-18
    • Seung-Won LeeSeung-Keun Lee
    • Seung-Won LeeSeung-Keun Lee
    • G12C16/00
    • G11C7/062G11C7/18G11C16/04G11C16/28G11C29/24G11C29/50004
    • A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.
    • 根据本发明的实施例的存储器件包括参考单元阵列和多个存储体。 每个银行都包含存储单元。 多个当前复印机电路分别对应于存储体。 每个当前复印机电路复制流过参考单元阵列的参考电流以产生参考电压。 多个感测块分别对应于存储体。 每个感测块包括多个读出放大器,用于响应于来自相应的当前复印机电路的参考电压来感测来自相应存储体的数据。 存储单元布局区域减少,感测速度提高。