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1. 发明授权

US08054688B2 Non-volatile memory device and erase method 有权
标题翻译：非易失性存储器件和擦除方法
公开(公告)号：US08054688B2
公开(公告)日：2011-11-08
申请号：US12539829
申请日：2009-08-12
申请人： Jae-hun Jeong , Soon-moon Jung , Han-soo Kim , Jae-hoon Jang
发明人： Jae-hun Jeong , Soon-moon Jung , Han-soo Kim , Jae-hoon Jang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483
摘要： Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.
摘要翻译：提供了一种非易失性存储器件，包括第一和第二垂直堆叠的半导体衬底，在第一和第二半导体衬底上形成为一行的多个非易失性存储单元晶体管，以及连接到第一和第二半导体衬底的栅极的多条字线多个非易失性存储单元晶体管。多个非易失性存储单元晶体管被分组成两个或更多个存储单元块，使得第一电压被施加到第一半导体衬底，该第一半导体衬底包括要擦除的第一存储单元块，以及（1）第二电压较小比不包括第一存储单元块的第二半导体衬底施加大于0V的第一电压，或者（2）不包括第一存储单元块的第二半导体衬底被电浮动。

2. 发明授权

US08040733B2 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08040733B2
公开(公告)日：2011-10-18
申请号：US12486924
申请日：2009-06-18
申请人： Jae-hun Jeong , Soon-moon Jung , Han-soo Kim , Jae-hoon Jang
发明人： Jae-hun Jeong , Soon-moon Jung , Han-soo Kim , Jae-hoon Jang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483
摘要： A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.
摘要翻译：非易失性存储器件包括分别连接到第一串存储单元晶体管的栅极的第一和第二串存储单元晶体管，相关的第一和第二字线，其中相应的第一和第二字线被连接以共同接收偏置电压。非易失性存储器件还包括连接到第一和第二串的虚拟单元晶体管，以及被配置为接收不同偏置电压的第一和第二虚拟字线。

3. 发明申请

US20160284729A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20160284729A1
公开(公告)日：2016-09-29
申请号：US15176917
申请日：2016-06-08
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： H01L27/115 , H01L23/528 , G11C16/10 , H01L23/522 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

4. 发明申请

US20110018036A1 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：垂直非易失性存储器件及其制造方法
公开(公告)号：US20110018036A1
公开(公告)日：2011-01-27
申请号：US12636912
申请日：2009-12-14
申请人： Sung-min Hwang , Han-soo Kim , Won-seok CHO , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
发明人： Sung-min Hwang , Han-soo Kim , Won-seok CHO , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
IPC分类号： H01L27/085
CPC分类号： G11C5/06 , H01L23/5283 , H01L27/112 , H01L27/115 , H01L27/11517
摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.
摘要翻译：垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线晶体管和字选择线的堆叠。每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。字选择线分别连接到集成字线。

5. 发明授权

US08492831B2 Vertical non-volatile memory device and method of fabricating the same 有权
标题翻译：垂直非易失性存储器件及其制造方法
公开(公告)号：US08492831B2
公开(公告)日：2013-07-23
申请号：US12636912
申请日：2009-12-14
申请人： Sung-min Hwang , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
发明人： Sung-min Hwang , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim , Jae-hun Jeong , Ki-hyun Kim
IPC分类号： H01L29/66
CPC分类号： G11C5/06 , H01L23/5283 , H01L27/112 , H01L27/115 , H01L27/11517
摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.
摘要翻译：垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线晶体管和字选择线的堆叠。每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。字选择线分别连接到集成字线。

6. 发明授权

US09478291B2 Non-volatile memory device having vertical structure and method of operating the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US09478291B2
公开(公告)日：2016-10-25
申请号：US15176917
申请日：2016-06-08
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
摘要翻译：具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。多个字线耦合到NAND串的多个存储单元。第一选择线通常连接到NAND串的至少一对第一选择晶体管。

7. 发明申请

US20130044545A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20130044545A1
公开(公告)日：2013-02-21
申请号：US13658461
申请日：2012-10-23
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
摘要翻译：具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。多个字线耦合到NAND串的多个存储单元。第一选择线通常连接到NAND串的至少一对第一选择晶体管。

8. 发明申请

US20140293703A1 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20140293703A1
公开(公告)日：2014-10-02
申请号：US14302025
申请日：2014-06-11
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
摘要翻译：具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。多个字线耦合到NAND串的多个存储单元。第一选择线通常连接到NAND串的至少一对第一选择晶体管。

9. 发明申请

US20110227141A1 NON-VOLATILE MEMORY DEVICES HAVING VERTICAL CHANNEL STRUCTURES AND RELATED FABRICATION METHODS 审中-公开
标题翻译：具有垂直通道结构的非易失性存储器件及相关制造方法
公开(公告)号：US20110227141A1
公开(公告)日：2011-09-22
申请号：US13048649
申请日：2011-03-15
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： A memory device having a vertical channel structure is disclosed. The memory device includes a plurality of gate lines extending substantially parallel to one another along a surface of a substrate, and a connection unit electrically connecting the plurality of gate lines. The connection unit includes a first portion laterally extending along the surface of the substrate, a second portion extending substantially perpendicular to the surface of the substrate, and a supporting insulating layer extending in a cavity defined by the first and second portions of the connection unit. Related fabrication methods are also discussed.
摘要翻译：公开了一种具有垂直通道结构的存储器件。存储器件包括沿衬底的表面基本上彼此平行延伸的多条栅极线，以及电连接多个栅极线的连接单元。连接单元包括沿基板的表面横向延伸的第一部分，基本上垂直于基板的表面延伸的第二部分，以及在由连接单元的第一和第二部分限定的空腔中延伸的支撑绝缘层。还讨论了相关制造方法。

10. 发明申请

US20100195395A1 Non-volatile memory device having vertical structure and method of operating the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其操作方法
公开(公告)号：US20100195395A1
公开(公告)日：2010-08-05
申请号：US12658072
申请日：2010-02-02
申请人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
发明人： Jae-hun Jeong , Han-soo Kim , Won-seok Cho , Jae-hoon Jang , Sun-il Shim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
摘要翻译：具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。多个字线耦合到NAND串的多个存储单元。第一选择线通常连接到NAND串的至少一对第一选择晶体管。

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