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    • 4. 发明授权
    • Apparatus and method for computing LLR
    • 用于计算LLR的装置和方法
    • US07917834B2
    • 2011-03-29
    • US11635366
    • 2006-12-07
    • Jong Hyun SeoByung Jo KimSeong Su Park
    • Jong Hyun SeoByung Jo KimSeong Su Park
    • H03M13/00
    • H03M13/3927H03M13/395H03M13/6502
    • Provided are an apparatus and method for efficiently computing a log likelihood ratio (LLR) using the maximum a posteriori (MAP) algorithm known as block combining. The method includes the steps of: calculating alpha values, beta values and gamma values of at least two time sections; calculating transition probabilities of respective states in the at least two time sections; performing a comparison operation for some of the transition probabilities to determine the highest value, selecting one of the other transition probabilities according to the determined high value, comparing the determined value with the selected value to select the higher value, and thereby obtaining the highest of the transition probabilities; and determining an operation to apply according to the highest transition probability and calculating an LLR.
    • 提供了一种使用称为块组合的最大后验(MAP)算法来有效地计算对数似然比(LLR)的装置和方法。 该方法包括以下步骤:计算至少两个时间段的α值,β值和γ值; 计算所述至少两个时间段中的各个状态的转移概率; 对一些转移概率进行比较操作以确定最高值,根据确定的高值选择其他转移概率之一,将所确定的值与所选择的值进行比较以选择较高的值,从而获得最高的 转移概率; 并根据最高转移概率确定应用的运算并计算LLR。
    • 5. 发明申请
    • METHOD FOR MANUFACTURING THIN FILM TRANSISTOR
    • 制造薄膜晶体管的方法
    • US20130217192A1
    • 2013-08-22
    • US13881948
    • 2011-10-27
    • Jong Hyun Seo
    • Jong Hyun Seo
    • H01L29/786
    • H01L29/786G02F1/1368H01L27/1225H01L29/7869
    • A method for manufacturing a thin film transistor includes forming a semiconductor layer, a wiring layer and a patterned mask layer in sequence on a substrate on which a gate electrode and a gate insulating layer are formed; patterning the wiring layer and the semiconductor layer based on the patterned mask layer while irradiating external light; removing at least a part of the mask layer; forming a channel portion by etching the wiring layer while controlling irradiation of the external light. Further, the method for manufacturing the thin film transistor can obtain an improved structure by forming the semiconductor layer made of an oxide which reacts to external light irradiated thereto, thus capable of adjusting a selectivity between the semiconductor layer and the wiring layer.
    • 制造薄膜晶体管的方法包括在形成有栅电极和栅极绝缘层的基板上依次形成半导体层,布线层和图案化掩模层; 在照射外部光的同时,基于图案化掩模层图案化布线层和半导体层; 去除所述掩模层的至少一部分; 通过在控制外部光的照射的同时蚀刻布线层来形成沟道部分。 此外,制造薄膜晶体管的方法可以通过形成由与其照射的外部光反应的氧化物制成的半导体层来获得改进的结构,从而能够调节半导体层和布线层之间的选择性。
    • 6. 发明授权
    • Method for manufacturing thin film transistor
    • 制造薄膜晶体管的方法
    • US08871578B2
    • 2014-10-28
    • US13881948
    • 2011-10-27
    • Jong Hyun Seo
    • Jong Hyun Seo
    • H01L21/84H01L29/786H01L27/12G02F1/1368
    • H01L29/786G02F1/1368H01L27/1225H01L29/7869
    • A method for manufacturing a thin film transistor includes forming a semiconductor layer, a wiring layer and a patterned mask layer in sequence on a substrate on which a gate electrode and a gate insulating layer are formed; patterning the wiring layer and the semiconductor layer based on the patterned mask layer while irradiating external light; removing at least a part of the mask layer; forming a channel portion by etching the wiring layer while controlling irradiation of the external light. Further, the method for manufacturing the thin film transistor can obtain an improved structure by forming the semiconductor layer made of an oxide which reacts to external light irradiated thereto, thus capable of adjusting a selectivity between the semiconductor layer and the wiring layer.
    • 制造薄膜晶体管的方法包括在形成有栅电极和栅极绝缘层的基板上依次形成半导体层,布线层和图案化掩模层; 在照射外部光的同时,基于图案化掩模层图案化布线层和半导体层; 去除所述掩模层的至少一部分; 通过在控制外部光的照射的同时蚀刻布线层来形成沟道部分。 此外,制造薄膜晶体管的方法可以通过形成由与其照射的外部光反应的氧化物制成的半导体层来获得改进的结构,从而能够调节半导体层和布线层之间的选择性。