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1. 发明授权

US07903069B2 LCD driver integrated circuit having double column structure 失效
标题翻译： LCD驱动器集成电路具有双列结构
公开(公告)号：US07903069B2
公开(公告)日：2011-03-08
申请号：US11467597
申请日：2006-08-28
申请人： Jae-Wook Kwon , Seung-Jung Lee
发明人： Jae-Wook Kwon , Seung-Jung Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2320/0276
摘要： A driver integrated circuit (IC) for a liquid crystal display (LCD) has a double column structure. The driver IC includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores first and second group channel data in response to a clock signal generated by the first shift register unit. The first decoder receives the first group channel data and outputs gamma voltages corresponding to the first group channel data. The second decoder receives the second group channel data and outputs gamma voltages corresponding to the second group channel data. The first and second output buffers are aligned along a long edge of the driver IC and buffer the corresponding gamma voltages to drive corresponding channels. The first shift register unit and the first data latch unit are shared by upper and lower blocks to process the first and second group channel data together.
摘要翻译：用于液晶显示器（LCD）的驱动器集成电路（IC）具有双列结构。驱动器IC包括第一移位寄存器单元，第一数据锁存单元，第一和第二解码器以及第一和第二输出缓冲器。第一数据锁存单元响应于由第一移位寄存器单元产生的时钟信号而接收并存储第一和第二组信道数据。第一解码器接收第一组信道数据并输出与第一组信道数据相对应的伽马电压。第二解码器接收第二组信道数据并输出对应于第二组信道数据的伽马电压。第一和第二输出缓冲器沿着驱动器IC的长边对准，并且缓冲相应的伽马电压以驱动相应的通道。第一移位寄存器单元和第一数据锁存单元由上下块共享以一起处理第一和第二组信道数据。

2. 发明申请

US20070140014A1 LCD Driver Integrated Circuit Having Double Column Structure 失效
标题翻译：具有双列结构的LCD驱动器集成电路
公开(公告)号：US20070140014A1
公开(公告)日：2007-06-21
申请号：US11467597
申请日：2006-08-28
申请人： Jae-Wook Kwon , Seung-Jung Lee
发明人： Jae-Wook Kwon , Seung-Jung Lee
IPC分类号： G11C11/34
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2320/0276
摘要： A driver integrated circuit (IC) for a liquid crystal display (LCD) has a double column structure. The driver IC includes a first shift register unit, a first data latch unit, first and second decoders, and first and second output buffers. The first data latch unit receives and stores first and second group channel data in response to a clock signal generated by the first shift register unit. The first decoder receives the first group channel data and outputs gamma voltages corresponding to the first group channel data. The second decoder receives the second group channel data and outputs gamma voltages corresponding to the second group channel data. The first and second output buffers are aligned along a long edge of the driver IC and buffer the corresponding gamma voltages to drive corresponding channels. The first shift register unit and the first data latch unit are shared by upper and lower blocks to process the first and second group channel data together.
摘要翻译：用于液晶显示器（LCD）的驱动器集成电路（IC）具有双列结构。驱动器IC包括第一移位寄存器单元，第一数据锁存单元，第一和第二解码器以及第一和第二输出缓冲器。第一数据锁存单元响应于由第一移位寄存器单元产生的时钟信号而接收并存储第一和第二组信道数据。第一解码器接收第一组信道数据并输出与第一组信道数据相对应的伽马电压。第二解码器接收第二组信道数据并输出对应于第二组信道数据的伽马电压。第一和第二输出缓冲器沿着驱动器IC的长边对准，并且缓冲相应的伽马电压以驱动相应的通道。第一移位寄存器单元和第一数据锁存单元由上下块共享以一起处理第一和第二组信道数据。

3. 发明申请

US20080109605A1 IMAGE DATA DRIVING APPARATUS AND METHOD OF REDUCING PEAK CURRENT 有权
标题翻译：图像数据驱动装置和降低峰值电流的方法
公开(公告)号：US20080109605A1
公开(公告)日：2008-05-08
申请号：US11756030
申请日：2007-05-31
申请人： Jae-Hong KO , Seung-Jung Lee
发明人： Jae-Hong KO , Seung-Jung Lee
IPC分类号： G06F12/00
CPC分类号： G09G3/20 , G09G2300/08 , G09G2310/027 , G09G2310/0289
摘要： A source driver includes a hold memory block, a pre-decoding block, a level shifting block and digital-to-analog (DAG) block. The hold memory block stores digital image data. The pre-decoding block generates a data code that includes at least one bit having a first logic level based on the digital image data and generates a plurality of enable signals based on the data code. The level shifting block performs level shifting of the data code based on the enable signals. The DAC block outputs a grayscale voltage that is selected based on the level shifted data code output from the level shifting block. A source driver module and a display device include a plurality of the source drivers.
摘要翻译：源驱动器包括保持存储器块，预解码块，电平移位块和数模（DAG）块。保持存储块存储数字图像数据。预解码块基于数字图像数据生成包括具有第一逻辑电平的至少一个比特的数据码，并且基于数据码产生多个使能信号。电平移位块基于使能信号执行数据代码的电平移位。 DAC块输出基于从电平移位块输出的电平移位数据代码选择的灰度电压。源驱动器模块和显示装置包括多个源驱动器。

4. 发明授权

US07295047B2 Output buffer with improved slew rate and method thereof 有权
标题翻译：输出缓冲器，具有改进的压摆率及其方法
公开(公告)号：US07295047B2
公开(公告)日：2007-11-13
申请号：US11319232
申请日：2005-12-28
申请人： Seung-Jung Lee , Do-Youn Kim , Chang-Hwe Choi
发明人： Seung-Jung Lee , Do-Youn Kim , Chang-Hwe Choi
IPC分类号： H03B1/00
CPC分类号： G09G3/3688 , G09G2310/0291 , H03K19/01721
摘要： An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output node to a control voltage in response to the control signal and a bias voltage. The output unit may maintain the first output signal between a given voltage and the control voltage based on the pull signal and the bias voltage.
摘要翻译：具有改进的压摆率的输出缓冲器及其方法。输出缓冲器可以包括差分放大器，控制器和输出单元。输出缓冲器可以基于接收到的输入和输出信号产生拉动信号和控制信号。控制器可以响应于控制信号和偏置电压而将输出节点转换到控制电压。输出单元可以基于拉动信号和偏置电压来保持给定电压和控制电压之间的第一输出信号。

5. 发明授权

US07952572B2 Image data driving apparatus and method of reducing peak current 有权
标题翻译：降低峰值电流的图像数据驱动装置和方法
公开(公告)号：US07952572B2
公开(公告)日：2011-05-31
申请号：US11756030
申请日：2007-05-31
申请人： Jae-Hong Ko , Seung-Jung Lee
发明人： Jae-Hong Ko , Seung-Jung Lee
IPC分类号： G09G5/00
CPC分类号： G09G3/20 , G09G2300/08 , G09G2310/027 , G09G2310/0289
摘要： A source driver includes a hold memory block, a pre-decoding block, a level shifting block and digital-to-analog (DAC) block. The hold memory block stores digital image data. The pre-decoding block generates a data code that includes at least one bit having a first logic level based on the digital image data and generates a plurality of enable signals based on the data code. The level shifting block performs level shifting of the data code based on the enable signals. The DAC block outputs a grayscale voltage that is selected based on the level shifted data code output from the level shifting block. A source driver module and a display device include a plurality of the source drivers.
摘要翻译：源驱动器包括保持存储器块，预解码块，电平移位块和数模（DAC）块。保持存储块存储数字图像数据。预解码块基于数字图像数据生成包括具有第一逻辑电平的至少一个比特的数据码，并且基于数据码产生多个使能信号。电平移位块基于使能信号执行数据代码的电平移位。 DAC块输出基于从电平移位块输出的电平移位数据代码选择的灰度电压。源驱动器模块和显示装置包括多个源驱动器。

6. 发明申请

US20060170458A1 Output buffer with improved slew rate and method thereof 有权
标题翻译：输出缓冲器，具有改进的压摆率及其方法
公开(公告)号：US20060170458A1
公开(公告)日：2006-08-03
申请号：US11319232
申请日：2005-12-28
申请人： Seung-Jung Lee , Do-Youn Kim , Chang-Hwe Choi
发明人： Seung-Jung Lee , Do-Youn Kim , Chang-Hwe Choi
IPC分类号： H03K19/094
CPC分类号： G09G3/3688 , G09G2310/0291 , H03K19/01721
摘要： An output buffer with an improved slew rate and method thereof. The output buffer may include a differential amplifier, a controller and an output unit. The output buffer may generate a pull signal and a control signal based on received input and output signals. The controller may transition an output node to a control voltage in response to the control signal and a bias voltage. The output unit may maintain the first output signal between a given voltage and the control voltage based on the pull signal and the bias voltage.
摘要翻译：具有改进的压摆率的输出缓冲器及其方法。输出缓冲器可以包括差分放大器，控制器和输出单元。输出缓冲器可以基于接收到的输入和输出信号产生拉动信号和控制信号。控制器可以响应于控制信号和偏置电压而将输出节点转换到控制电压。输出单元可以基于拉动信号和偏置电压来保持给定电压和控制电压之间的第一输出信号。

7. 发明申请

US20070091054A1 Slew rate adjusting circuit, source driver, source driver module, and display device 审中-公开
标题翻译：压摆率调节电路，源极驱动器，源极驱动器模块和显示器件
公开(公告)号：US20070091054A1
公开(公告)日：2007-04-26
申请号：US11583087
申请日：2006-10-19
申请人： Seung-Jung Lee
发明人： Seung-Jung Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/08 , G11C19/00 , G11C19/28
摘要： Provided is a slew rate adjusting circuit, a source driver, a source driver module and a display device. The slew rate adjusting circuit may output a buffered signal, in response to an input signal input to an Mth stage shift register, where M is a natural number less than N, from a last stage of the N stage cascade shift register and a reference voltage output from a reference voltage generator, a slew rate of the buffered signal depending on a level of the reference voltage. The source driver may include an N stage cascade shift register, a reference voltage generator, a slew rate adjusting circuit, and/or a latch. The N stage cascade shift register may sequentially shift a start pulse driving the source driver in response to a clock signal. The reference voltage generator may generate a reference voltage. The slew rate adjusting circuit, in response to an input signal inputted to the Mth stage shift register, where M is a natural number smaller than N, from a last stage of the N stage cascade shift register and the reference voltage output from the reference voltage generator, may buffer the input signal and output a buffered signal. The slew rate of the buffered signal may be adjusted based on a level of the reference voltage. The latch may latch a signal output from the slew rate adjusting circuit in response to the clock signal. The source driver module may include a plurality of source drivers. The display device may include a display panel, a gate driver, and a source driver module.
摘要翻译：提供了一种压摆率调整电路，源极驱动器，源极驱动器模块和显示器件。转换速率调整电路可以响应于输入到第M级移位寄存器的输入信号，其中M是小于N的自然数，从N的最后阶段输出缓冲信号级级联移位寄存器和参考电压发生器的参考电压输出，缓冲信号的转换速率取决于参考电压的电平。源极驱动器可以包括N级级联移位寄存器，参考电压发生器，压摆率调整电路和/或锁存器。 N级级联移位寄存器可以响应于时钟信号顺序地移动驱动源极驱动器的起始脉冲。参考电压发生器可产生参考电压。转换速率调整电路响应于输入到第M级级移位寄存器的输入信号，其中M是小于N的自然数，从N级级联移位寄存器的最后级和从参考电压发生器输出的参考电压可以缓冲输入信号并输出缓冲信号。可以基于参考电压的电平来调整缓冲信号的转换速率。锁存器可以响应于时钟信号锁存从压摆率调整电路输出的信号。源驱动器模块可以包括多个源驱动器。显示装置可以包括显示面板，门驱动器和源驱动器模块。

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