会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Gate driving circuit and display device having the gate driving circuit
    • 栅极驱动电路和具有栅极驱动电路的显示装置
    • US08243058B2
    • 2012-08-14
    • US12616604
    • 2009-11-11
    • Jae-Hoon LeeJun-Yong SongHoi-Sik MoonYong-Soon Lee
    • Jae-Hoon LeeJun-Yong SongHoi-Sik MoonYong-Soon Lee
    • G06F3/038
    • G09G3/3677G09G2310/0286G11C19/184G11C19/28
    • A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.
    • 栅极驱动电路包括彼此连接的多个级。 第m级(“m”是自然数)级包括上拉部分,下拉部分,第一保持部分和第二保持部分。 响应于施加到第一输出控制部分的高电压,上拉部分输出作为第m门信号的高电压的时钟信号的高电压。 下拉部分响应于第(m + 1)门信号的高电压将第m门信号的高电压下拉到第一低电压。 第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。 第二保持部将第m栅极信号的低电压保持为第一低电压。
    • 2. 发明申请
    • Gate Driving Circuit and Display Device Having the Gate Driving Circuit
    • 具有栅极驱动电路的栅极驱动电路和显示装置
    • US20100207928A1
    • 2010-08-19
    • US12616604
    • 2009-11-11
    • Jae-Hoon LeeJun-Yong SongHoi-Sik MoonYong-Soon Lee
    • Jae-Hoon LeeJun-Yong SongHoi-Sik MoonYong-Soon Lee
    • G09G5/00
    • G09G3/3677G09G2310/0286G11C19/184G11C19/28
    • A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.
    • 栅极驱动电路包括彼此连接的多个级。 第m级(“m”是自然数)级包括上拉部分,下拉部分,第一保持部分和第二保持部分。 响应于施加到第一输出控制部分的高电压,上拉部分输出作为第m门信号的高电压的时钟信号的高电压。 下拉部分响应于第(m + 1)门信号的高电压将第m门信号的高电压下拉到第一低电压。 第一保持部分将施加到第一输出控制部分的电压保持为具有低于第一低电压电平的第二低电压。 第二保持部将第m栅极信号的低电压保持为第一低电压。