专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120139883A1 GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：门控驱动电路和显示装置
公开(公告)号：US20120139883A1
公开(公告)日：2012-06-07
申请号：US13292661
申请日：2011-11-09
申请人： Jae-Hoon LEE , Young-Su KIM , Whee-Won LEE , Jun-Yong SONG , Yu-Han BAE , You-Mee HYUN
发明人： Jae-Hoon LEE , Young-Su KIM , Whee-Won LEE , Jun-Yong SONG , Yu-Han BAE , You-Mee HYUN
IPC分类号： G06F3/038 , H03K3/00
CPC分类号： G09G3/3611 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041 , G11C19/28
摘要： A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.
摘要翻译：栅极驱动电路包括其中多级级联连接的移位寄存器。在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。

2. 发明申请

US20120146985A1 METHOD OF DRIVING DISPLAY PANEL AND DISPLAY APPARATUS FOR PERFORMING THE SAME 有权
标题翻译：驱动显示面板的方法和执行其的显示装置
公开(公告)号：US20120146985A1
公开(公告)日：2012-06-14
申请号：US13180749
申请日：2011-07-12
申请人： Whee-Won LEE , Seung-Hwan MOON , Jae-Hoon LEE , Jun-Yong SONG
发明人： Whee-Won LEE , Seung-Hwan MOON , Jae-Hoon LEE , Jun-Yong SONG
IPC分类号： G09G5/00 , G09G3/10
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3677 , G09G2300/0426 , G09G2310/0281
摘要： A method of driving a display panel includes generating a gate on voltage, generating first and second gate off voltages based on an external voltage in a first operating mode, and first and second gate off voltages based on the gate on voltage in a second operating mode, generating a clock signal based on the gate on voltage and the second gate off voltage and outputting a gate voltage generated based on the clock signal and the first and second gate off voltages to a gate line of the display panel.
摘要翻译：驱动显示面板的方法包括：产生栅极导通电压，基于第一操作模式中的外部电压产生第一和第二栅极截止电压，以及基于第二工作模式中的栅极导通电压的第一和第二栅极截止电压基于栅极导通电压和第二栅极截止电压产生时钟信号，并将基于时钟信号和第一和第二栅极截止电压产生的栅极电压输出到显示面板的栅极线。

3. 发明申请

US20120162187A1 GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：门控驱动电路和显示装置
公开(公告)号：US20120162187A1
公开(公告)日：2012-06-28
申请号：US13274939
申请日：2011-10-17
申请人： Jae-Hoon LEE , Chang-Ho LEE , Jun-Yong SONG , Yu-Han BAE
发明人： Jae-Hoon LEE , Chang-Ho LEE , Jun-Yong SONG , Yu-Han BAE
IPC分类号： G09G5/00 , H03B1/00
CPC分类号： G09G3/007 , G09G3/29 , G09G2300/0838 , G09G2300/0871 , G09G2310/0286 , G09G2310/0289
摘要： A gate drive circuit includes a plurality of driving stages. An n-th (‘n’ is a natural number) driving stage includes a pull-up part, a carry part, a first pull-down part, a first pull-up/down control part and a second pull-up/down control part. The first pull-up/down control part applies a first power signal of an ON voltage to a control terminal of the pull-up part in a forward direction mode, and applies the first power signal of a second OFF voltage to a control terminal of the pull-up part in a reverse direction mode. The second pull-up/down control part applies a second power signal of the second OFF voltage to the control terminal of the pull-up part in the forward direction mode, and applies the second power signal of the ON voltage to the control terminal of the pull-up part in the reverse direction mode.
摘要翻译：栅极驱动电路包括多个驱动级。第n（'n'是自然数）驱动级包括上拉部分，进位部分，第一下拉部分，第一上拉/下拉控制部分和第二上拉/下拉控制部分。第一上拉/下拉控制部分向前向模式向上拉部分的控制端施加导通电压的第一电源信号，并将第二OFF电压的第一电源信号施加到上拉部分处于反向模式。第二上拉/下拉控制部分将第二OFF电压的第二功率信号以正向模式施加到上拉部分的控制端，并将接通电压的第二功率信号施加到上拉部分处于反向模式。

4. 发明申请

US20130038587A1 SCAN DRIVER, DISPLAY DEVICE INCLUDING THE SAME, AND DRIVING METHOD THEREOF 审中-公开
标题翻译：扫描驱动器，包括其的显示装置及其驱动方法
公开(公告)号：US20130038587A1
公开(公告)日：2013-02-14
申请号：US13301086
申请日：2011-11-21
申请人： Jun-Yong SONG , Jae Hoon Lee
发明人： Jun-Yong SONG , Jae Hoon Lee
IPC分类号： G09G5/00
CPC分类号： G09G5/18 , G09G3/20 , G09G2300/0408 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/08
摘要： A scan driver includes stages dependently connected to each other, where each of the stages outputs a gate signal, where a first scanning start signal is input to a first stage of the stages, where a second scanning start signal is input to a last stage of the stages, where each of the first scanning start signal and the second scanning start signal has one pulse per frame, where the stages sequentially output a gate-on voltage between a time when a pulse of the first scanning start signal for a frame is input to the first stage and a time when a pulse of the second scanning start signal for the frame is input to the last stage, and where the stages output a first low voltage lower than the gate-on voltage after the pulse of the second scanning start signal for the frame is input to the last stage.
摘要翻译：扫描驱动器包括依赖于彼此连接的级，其中每个级输出门信号，其中第一扫描开始信号被输入到级的第一级，其中第二扫描开始信号被输入到最后级其中第一扫描开始信号和第二扫描开始信号中的每一个每帧具有一个脉冲，其中级在输入帧的第一扫描开始信号的脉冲的时间之间顺序地输出栅极导通电压到第一级，并且将帧的第二扫描开始信号的脉冲输入到最后级的时间，并且其中级在第二扫描开始的脉冲之后输出低于栅极导通电压的第一低电压帧的信号被输入到最后阶段。

5. 发明申请

US20090257537A1 DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION 审中-公开
标题翻译：在数据传输期间最小化抖动的半导体存储器的数据恢复电路
公开(公告)号：US20090257537A1
公开(公告)日：2009-10-15
申请号：US12344736
申请日：2008-12-29
申请人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
发明人： Yong-Ju KIM , Hae-Rang CHOI , Oh-Kyong KWON , Jun-Yong SONG , Min-Seok SHIN
IPC分类号： H04L7/00
CPC分类号： H04L7/0338 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C7/222 , H03K5/135
摘要： A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data.
摘要翻译：呈现数据传输中抖动最小化的数据恢复电路。数据恢复电路包括数据分割单元，数据采样单元，数据选择单元和数据恢复单元。数据分割单元用于分割外部数据以产生多分割数据。数据采样单元用于在第一时间和第二时间对多分割数据进行采样以产生采样数据。数据选择单元用于根据抽样数据是否被转换以输出所选择的数据作为选择数据，用于从采样数据中选择在第一时间或第二时间采样的数据中的一个。数据恢复单元用于将选择数据恢复到与外部数据的逻辑电平相同的逻辑电平的内部数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式