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1. 发明申请

US20120034784A1 Methods of Forming Fine Patterns in Semiconductor Devices 有权
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US20120034784A1
公开(公告)日：2012-02-09
申请号：US13242504
申请日：2011-09-23
申请人： Jae-Ho Min , O-lk Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-lk Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/308
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.
摘要翻译：形成半导体器件的方法可以包括提供具有第一区域和第二区域的特征层。所述方法还可以包括在特征层上形成双掩模层。所述方法还可以包括在双掩模层上形成可变掩模层。所述方法还可以包括通过对可变掩模层和双掩模层进行构图来在第一区域中的特征层上形成第一结构和在第二区域中的特征层上形成第二结构。所述方法还可以包括在第一结构的侧壁上形成第一间隔物，在第二结构的侧壁上形成第二间隔物。所述方法还可以包括在保持第二结构的至少一部分的同时移除第一结构。

2. 发明授权

US08637407B2 Methods of forming fine patterns in semiconductor devices 有权
公开(公告)号：US08637407B2
公开(公告)日：2014-01-28
申请号：US13242504
申请日：2011-09-23
申请人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

3. 发明授权

US08110506B2 Methods of forming fine patterns in semiconductor devices 有权
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US08110506B2
公开(公告)日：2012-02-07
申请号：US12428963
申请日：2009-04-23
申请人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.
摘要翻译：可以通过使用自对准反向图案化来同时形成多个掩模图案来提供形成半导体器件的方法，包括具有不同宽度的各个掩模图案元件。

4. 发明申请

US20100055914A1 METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US20100055914A1
公开(公告)日：2010-03-04
申请号：US12428963
申请日：2009-04-23
申请人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
发明人： Jae-Ho Min , O-Ik Kwon , Bum-Soo Kim , Dong-chan Kim , Myeong-cheol Kim
IPC分类号： H01L21/308
CPC分类号： G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.
摘要翻译：可以通过使用自对准反向图案化来同时形成多个掩模图案来提供形成半导体器件的方法，包括具有不同宽度的各个掩模图案元件。

5. 发明授权

US08310055B2 Semiconductor devices having narrow conductive line patterns and related methods of forming such semiconductor devices 有权
标题翻译：具有窄导线图形的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US08310055B2
公开(公告)日：2012-11-13
申请号：US12645820
申请日：2009-12-23
申请人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
发明人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L23/522 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.
摘要翻译：提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

6. 发明申请

US20100155959A1 Semiconductor Devices Having Narrow Conductive Line Patterns and Related Methods of Forming Such Semiconductor Devices 有权
标题翻译：具有窄导电线图案的半导体器件和形成这种半导体器件的相关方法
公开(公告)号：US20100155959A1
公开(公告)日：2010-06-24
申请号：US12645820
申请日：2009-12-23
申请人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
发明人： Young-ju Park , Jae-ho Min , Myeong-cheol Kim , Dong-chan Kim , Jae-hwang Sim
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L23/522 , H01L27/0207 , H01L27/11519 , H01L27/11531 , H01L27/11548 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.
摘要翻译：提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

7. 发明授权

US09054051B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09054051B2
公开(公告)日：2015-06-09
申请号：US13473091
申请日：2012-05-16
申请人： Soo-yeon Jeong , In-ho Kim , Hyung-yong Kim , Myeong-cheol Kim
发明人： Soo-yeon Jeong , In-ho Kim , Hyung-yong Kim , Myeong-cheol Kim
IPC分类号： H01L21/311 , H01L27/102 , H01L49/02 , H01L45/00 , H01L27/24 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76816 , H01L21/76898 , H01L27/1021 , H01L27/2409 , H01L28/91 , H01L45/06 , H01L45/1233 , H01L45/1683
摘要： In a method of fabricating a semiconductor device, a target layer and a first material layer are sequentially formed on a substrate. A plurality of second material layer patterns are formed on the first material layer, the second material layer patterns extending in a first horizontal direction. A plurality of hardmask patterns extending in a second horizontal direction are formed on the plurality of second material layer patterns and the first material layer, wherein the second horizontal direction is different from the first horizontal direction. A first material layer pattern is formed by etching the first material layer using the plurality of hardmask patterns and the plurality of second material layer patterns as etch masks. A target layer pattern with a plurality of holes is formed by etching the target layer using the first material layer pattern as an etch mask.
摘要翻译：在制造半导体器件的方法中，目标层和第一材料层依次形成在衬底上。在第一材料层上形成多个第二材料层图案，第二材料层图案沿第一水平方向延伸。在多个第二材料层图案和第一材料层上形成有沿第二水平方向延伸的多个硬掩模图案，其中第二水平方向与第一水平方向不同。通过使用多个硬掩模图案和多个第二材料层图案作为蚀刻掩模蚀刻第一材料层来形成第一材料层图案。通过使用第一材料层图案作为蚀刻掩模蚀刻目标层来形成具有多个孔的目标层图案。

8. 发明授权

US09048192B2 Method of forming a pattern 有权
标题翻译：形成图案的方法
公开(公告)号：US09048192B2
公开(公告)日：2015-06-02
申请号：US13493146
申请日：2012-06-11
申请人： Dong-kwon Kim , Ki-il Kim , Ah-young Cheon , Myeong-cheol Kim , Yong-jin Kim
发明人： Dong-kwon Kim , Ki-il Kim , Ah-young Cheon , Myeong-cheol Kim , Yong-jin Kim
IPC分类号： H01L21/00 , H01L21/3065 , H01L21/308
CPC分类号： H01L23/5283 , H01L21/3065 , H01L21/30655 , H01L21/3086 , H01L21/32139 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.
摘要翻译：形成图案的方法包括在基板上形成掩模图案; 通过深反应离子蚀刻（DRIE）蚀刻衬底并通过使用掩模图案作为蚀刻掩模; 部分地去除所述掩模图案以暴露所述基板的上表面的一部分; 并蚀刻衬底的上表面的暴露部分。在该方法中，当由DRIE形成图案时，图案的上部不突出或几乎不突出，并且图案的侧壁的扇形光滑，因此可以容易地在保护层的表面上形成共形材料层模式。

9. 发明授权

US07601647B2 Method of forming fine patterns of semiconductor device using double patterning 有权
标题翻译：使用双重图案形成半导体器件精细图案的方法
公开(公告)号：US07601647B2
公开(公告)日：2009-10-13
申请号：US11810200
申请日：2007-06-05
申请人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
发明人： Kyung-yub Jeon , Myeong-cheol Kim , Hak-sun Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32137
摘要： A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.
摘要翻译：形成半导体器件的精细图案的方法包括通过改变产生聚合物副产物的量来双重蚀刻，以在具有不同图案密度的区域中蚀刻具有不同厚度的膜。在第一蚀刻中，在第一蚀刻环境下，在低密度图案区域和高密度图案区域中的缓冲层和硬掩模层上执行反应离子蚀刻（RIE），直到蚀刻膜暴露于低使用掩模图案作为蚀刻掩模的密度图案区域。在用于形成硬掩模图案的第二蚀刻中，使用掩模图案作为蚀刻掩模，硬掩模层被蚀刻直到蚀刻膜在高密度图案区域中暴露，同时在低密度图案区域中的蚀刻膜上聚集聚合物副产物，在第二蚀刻环境下具有比在第一蚀刻环境中产生的聚合物副产物大的密度图案区域。

10. 发明授权

US06385020B1 Methods of forming HSG capacitors from nonuniformly doped amorphous silicon layers and HSG capacitors formed thereby 失效
标题翻译：由不均匀掺杂的非晶硅层和由此形成的HSG电容器形成HSG电容器的方法
公开(公告)号：US06385020B1
公开(公告)日：2002-05-07
申请号：US09487740
申请日：2000-01-19
申请人： Hyun-bo Shin , Myeong-cheol Kim , Jin-won Kim , Ki-hyun Hwang , Jae-young Park , Bon-young Koo
发明人： Hyun-bo Shin , Myeong-cheol Kim , Jin-won Kim , Ki-hyun Hwang , Jae-young Park , Bon-young Koo
IPC分类号： H02H700
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/84
摘要： A hemispherical grain (HSG) capacitor having HSGs on at least a part of the surface of capacitor lower electrodes, and a method of forming the same. In the capacitor, lower electrodes are formed of at least two amorphous silicon layers including an amorphous silicon layer doped with a high concentration of impurities and an amorphous silicon layer doped with a low concentration of impurities, and HSGs are formed, wherein the size of the hemispherical grains can be adjusted such that the size of HSGs formed on the inner surface of a U-shaped lower electrode or on the top of a stacked lower electrode is larger than that of HSGs formed on the outer surface of the U-shaped lower electrode or on the sidews of the stacked lower electrode. Thus, bridging between neighboring lower electrodes can be avoided by appropriately adjusting the size of HSGs, resulting in uniform capacitance wafer-to-wafer and within a wafer. The mechanical strength of the U-shaped lower electrode can also be enhanced.
摘要翻译：在电容器下电极的表面的至少一部分上具有HSG的半球状晶粒（HSG）电容器及其形成方法。在电容器中，下电极由至少两个非晶硅层形成，包括掺杂有高浓度杂质的非晶硅层和掺杂有低浓度杂质的非晶硅层，形成HSG，可以调节半球形颗粒，使得形成在U形下电极的内表面上或堆叠的下电极的顶部上的HSG的尺寸大于形成在U形下电极的外表面上的HSG的尺寸或在堆叠的下电极的侧面上。因此，可以通过适当地调节HSG的尺寸来避免相邻的下部电极之间的桥接，导致晶片到晶片和晶片内的均匀电容。也可以提高U形下电极的机械强度。

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