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1. 发明授权

US07244649B2 Method of manufacturing a capacitor having improved capacitance and method of manufacturing a semiconductor device including the capacitor 失效
标题翻译：制造具有改善电容的电容器的方法和制造包括该电容器的半导体器件的方法
公开(公告)号：US07244649B2
公开(公告)日：2007-07-17
申请号：US11007443
申请日：2004-12-09
申请人： Jae-Dong Lee , Chang-Ki Hong , Young-Rae Park
发明人： Jae-Dong Lee , Chang-Ki Hong , Young-Rae Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.
摘要翻译：公开了一种制造电容器的方法。使用蚀刻停止层或抛光停止层来保护电容器的存储电极在其制造期间被化学机械抛光工艺或回蚀工艺损坏。

2. 发明申请

US20050130385A1 Method of manufacturing a capacitor having improved capacitance and method of manufacturing a semiconductor device including the capacitor 失效
标题翻译：制造具有改善电容的电容器的方法和制造包括该电容器的半导体器件的方法
公开(公告)号：US20050130385A1
公开(公告)日：2005-06-16
申请号：US11007443
申请日：2004-12-09
申请人： Jae-Dong Lee , Chang-Ki Hong , Young-Rae Park
发明人： Jae-Dong Lee , Chang-Ki Hong , Young-Rae Park
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.
摘要翻译：公开了一种制造电容器的方法。使用蚀刻停止层或抛光停止层来保护电容器的存储电极在其制造期间被化学机械抛光工艺或回蚀工艺损坏。

3. 发明申请

US20050014330A1 Method of planarizing an interlayer dielectric layer 审中-公开
标题翻译：平面化层间电介质层的方法
公开(公告)号：US20050014330A1
公开(公告)日：2005-01-20
申请号：US10777864
申请日：2004-02-12
申请人： Young-Rae Park , Jae-Dong Lee , Joon Park , Chang-Ki Hong
发明人： Young-Rae Park , Jae-Dong Lee , Joon Park , Chang-Ki Hong
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10897 , H01L21/31053 , H01L21/76819 , H01L27/10817 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A method of planarizing an interlayer dielectric layer formed over a one cylinder storage (OCS) capacitor including applying two or three interlayer dielectric layers over the capacitor and planarizing the interlayer dielectric layers using CMP having a different etching selectivity according to the layers.
摘要翻译：平面化在单缸存储（OCS）电容器上形成的层间电介质层的方法，包括在电容器上施加两个或三个层间电介质层，并使用根据层的具有不同蚀刻选择性的CMP平坦化层间电介质层。

4. 发明申请

US20050272218A1 Method of forming metal lower electrode of a capacitor and method of selectively etching a metal layer for the same 审中-公开
标题翻译：形成电容器的金属下电极的方法及其选择性蚀刻金属层的方法
公开(公告)号：US20050272218A1
公开(公告)日：2005-12-08
申请号：US11145308
申请日：2005-06-03
申请人： Young-Rae Park , Young-Ho Koh , Chang-Ki Hong
发明人： Young-Rae Park , Young-Ho Koh , Chang-Ki Hong
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/20 , H01L21/8242 , H01L23/52 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/91
摘要： A method of forming a cylindrical lower electrode of a capacitor in which metal is used as a lower electrode of a capacitor. A metal capping layer is used in order to protect the inner walls of the cylindrical metal lower electrode. A sacrificial insulating layer is patterned to form an aperture for forming the lower electrode. A metal lower electrode layer and the metal capping layer are sequentially formed. In order to electrically separate adjacent metal lower electrodes from each other, the metal capping layer and the metal lower electrode layer are simultaneously planarized until the sacrificial insulating layer is exposed. The sacrificial insulating layer and the metal capping layer that resides in the aperture are removed such that the cylindrical metal lower electrode having inner and outer walls is completed. Therefore, it is possible to simultaneously palanarize the metal capping layer and the metal lower electrode layer with respect to the sacrificial insulating layer such that it is possible to simplify processes for forming the lower electrodes.
摘要翻译：一种形成电容器的圆柱形下电极的方法，其中金属用作电容器的下电极。为了保护圆柱形金属下电极的内壁，使用金属覆盖层。图案化牺牲绝缘层以形成用于形成下电极的孔。依次形成金属下电极层和金属覆盖层。为了将相邻的金属下电极彼此电分离，金属覆盖层和金属下电极层同时被平坦化，直到牺牲绝缘层暴露。除去驻留在孔中的牺牲绝缘层和金属覆盖层，使得具有内壁和外壁的圆柱形金属下电极完成。因此，可以相对于牺牲绝缘层同时进行金属覆盖层和金属下电极层的平坦化，使得可以简化用于形成下电极的工艺。

5. 发明授权

US06548388B2 Semiconductor device including gate electrode having damascene structure and method of fabricating the same 失效
公开(公告)号：US06548388B2
公开(公告)日：2003-04-15
申请号：US09805213
申请日：2001-03-14
申请人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
发明人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823437 , H01L21/823481
摘要： A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.

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