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1. 发明授权

US08451674B2 Clock synchronization in a memory system 有权
标题翻译：存储器系统中的时钟同步
公开(公告)号：US08451674B2
公开(公告)日：2013-05-28
申请号：US13446703
申请日：2012-04-13
申请人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
发明人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.
摘要翻译：在存储器系统中提供同步。在存储器写入操作期间，通过控制信号将定时参考信号发送到存储器件，并且从存储器件接收校准信号。根据校准信号调整内部时钟信号，然后根据内部时钟发送数据信号。以这种方式，数据被同步，使得数据根据本地时钟信号被精确地采样。

2. 发明申请

US20120262998A1 CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的时钟同步
公开(公告)号：US20120262998A1
公开(公告)日：2012-10-18
申请号：US13446703
申请日：2012-04-13
申请人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
发明人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.
摘要翻译：在存储器系统中提供同步。在存储器写入操作期间，通过控制信号将定时参考信号发送到存储器件，并且从存储器件接收校准信号。根据校准信号调整内部时钟信号，然后根据内部时钟发送数据信号。以这种方式，数据被同步，使得数据根据本地时钟信号被精确地采样。

3. 发明申请

US20100188910A1 CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的时钟同步
公开(公告)号：US20100188910A1
公开(公告)日：2010-07-29
申请号：US12596535
申请日：2008-04-18
申请人： Jade M. Kizer , John M. Wilson , John Eble III , Frederick A. Ware
发明人： Jade M. Kizer , John M. Wilson , John Eble III , Frederick A. Ware
IPC分类号： G11C7/22 , G11C8/18
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.
摘要翻译：用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。基于采样结果，数据选通和本地时钟信号同步。以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。

4. 发明授权

US08159887B2 Clock synchronization in a memory system 有权
标题翻译：存储器系统中的时钟同步
公开(公告)号：US08159887B2
公开(公告)日：2012-04-17
申请号：US12596535
申请日：2008-04-18
申请人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
发明人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.
摘要翻译：用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。基于采样结果，数据选通和本地时钟信号同步。以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。

5. 发明授权

US08581920B2 Utilizing masked data bits during accesses to a memory 有权
标题翻译：在访问存储器期间利用屏蔽的数据位
公开(公告)号：US08581920B2
公开(公告)日：2013-11-12
申请号：US12210104
申请日：2008-09-12
申请人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
发明人： Lei Luo , Frederick A. Ware , John Wilson , Jade M. Kizer
IPC分类号： G09G5/37 , G06T1/60
CPC分类号： G06F9/30018 , G09G5/363 , G09G5/393 , G09G2330/021 , G09G2330/06
摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.
摘要翻译：描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

6. 发明授权

US08243484B2 Adjustable width strobe interface 有权
标题翻译：可调宽度选通接口
公开(公告)号：US08243484B2
公开(公告)日：2012-08-14
申请号：US12532914
申请日：2008-03-27
申请人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
IPC分类号： G11C5/02
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.
摘要翻译：存储器系统包括电路板40，其包括N条数据信号线60,65和至少两个选通信号线70,75以及固定到电路板的相对表面40a，40b的第一和第二存储器件50,55。每个存储器件耦合到N个数据信号线的一部分和至少两个选通信号线的一部分，使得器件不共享N个数据信号线中的任何一个，并且使得器件不共享选通信号线。存储系统还包括控制器45，通过N个数据信号线和至少两个选通信号线与第一和第二存储器装置并行通信。

7. 发明申请

US20100103713A1 ADJUSTABLE WIDTH STROBE INTERFACE 有权
标题翻译：可调节宽度的界面
公开(公告)号：US20100103713A1
公开(公告)日：2010-04-29
申请号：US12532914
申请日：2008-03-27
申请人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.
摘要翻译：存储器系统包括电路板40，其包括N条数据信号线60,65和至少两个选通信号线70,75以及固定到电路板的相对表面40a，40b的第一和第二存储器件50,55。每个存储器件耦合到N个数据信号线的一部分和至少两个选通信号线的一部分，使得器件不共享N个数据信号线中的任何一个，并且使得器件不共享选通信号线。存储系统还包括控制器45，通过N个数据信号线和至少两个选通信号线与第一和第二存储器装置并行通信。

8. 发明授权

US08441872B2 Memory controller with adjustable width strobe interface 有权
标题翻译：内存控制器带可调宽度选通接口
公开(公告)号：US08441872B2
公开(公告)日：2013-05-14
申请号：US13552511
申请日：2012-07-18
申请人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihito Koya , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.
摘要翻译：公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

9. 发明授权

US08588280B2 Asymmetric communication on shared links 有权
标题翻译：共享链路上的不对称通信
公开(公告)号：US08588280B2
公开(公告)日：2013-11-19
申请号：US12809000
申请日：2008-12-19
申请人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
发明人： Kyung Suk Oh , John Wilson , Frederick A. Ware , WooPoung Kim , Jade M. Kizer , Brian S. Leibowitz , Lei Luo , John Cronan Eble
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述通过共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

10. 发明申请

US20130021857A1 MEMORY CONTROLLER WITH ADJUSTABLE WIDTH STROBE INTERFACE 有权
标题翻译：具有可调宽度结构界面的存储器控制器
公开(公告)号：US20130021857A1
公开(公告)日：2013-01-24
申请号：US13552511
申请日：2012-07-18
申请人： Jade M. Kizer , Yoshihiro Koya , Frederick A. Ware
发明人： Jade M. Kizer , Yoshihiro Koya , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G06F13/4239 , G11C5/02 , G11C5/04 , H05K1/0237 , H05K1/181 , H05K2201/10159 , Y02P70/611
摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.
摘要翻译：公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

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