专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09626191B2 Shaped register file reads 有权
公开(公告)号：US09626191B2
公开(公告)日：2017-04-18
申请号：US13335868
申请日：2011-12-22
申请人： Jack Hilaire Choquette , Michael Fetterman , Shirish Gadre , Xiaogang Qiu , Omkar Paranjape , Anjana Rajendran , Stewart Glenn Carlton , Eric Lyell Hill , Rajeshwaran Selvanesan , Douglas J. Hahn
发明人： Jack Hilaire Choquette , Michael Fetterman , Shirish Gadre , Xiaogang Qiu , Omkar Paranjape , Anjana Rajendran , Stewart Glenn Carlton , Eric Lyell Hill , Rajeshwaran Selvanesan , Douglas J. Hahn
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/3012
摘要： One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers.

2. 发明申请

US20130212364A1 PRE-SCHEDULED REPLAYS OF DIVERGENT OPERATIONS 审中-公开
标题翻译：预先安排的重复操作
公开(公告)号：US20130212364A1
公开(公告)日：2013-08-15
申请号：US13370173
申请日：2012-02-09
申请人： Michael FETTERMAN , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
发明人： Michael FETTERMAN , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency.
摘要翻译：本公开的一个实施例阐述了在并行处理子系统中执行用于发散操作的预先安排的重播操作的优化方式。具体地，流式多处理器（SM）包括多级流水线，其被配置为将预先安排的重播操作插入到多级流水线中。预先安排的重播单元检测与当前指令相关联的操作是否正在访问公共资源。如果线程正在访问分布在多个高速缓存线上的数据，则预先安排的重播单元在当前指令后面插入预先安排的重放操作。多级流水线顺序执行指令和相关的预先安排的重播操作。如果附加线程在执行指令和预先安排的重放操作之后保持未被接受，则通过重放循环插入附加的重放操作，直到对所有线程进行服务。所公开技术的一个优点是需要一个或多个重放操作的发散操作以较低的等待时间执行。

3. 发明授权

US10152329B2 Pre-scheduled replays of divergent operations 有权
公开(公告)号：US10152329B2
公开(公告)日：2018-12-11
申请号：US13370173
申请日：2012-02-09
申请人： Michael Fetterman , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
发明人： Michael Fetterman , Stewart Glenn Carlton , Jack Hilaire Choquette , Shirish Gadre , Olivier Giroux , Douglas J. Hahn , Steven James Heinrich , Eric Lyell Hill , Charles McCarver , Omkar Paranjape , Anjana Rajendran , Rajeshwaran Selvanesan
IPC分类号： G06F9/38
摘要： One embodiment of the present disclosure sets forth an optimized way to execute pre-scheduled replay operations for divergent operations in a parallel processing subsystem. Specifically, a streaming multiprocessor (SM) includes a multi-stage pipeline configured to insert pre-scheduled replay operations into a multi-stage pipeline. A pre-scheduled replay unit detects whether the operation associated with the current instruction is accessing a common resource. If the threads are accessing data which are distributed across multiple cache lines, then the pre-scheduled replay unit inserts pre-scheduled replay operations behind the current instruction. The multi-stage pipeline executes the instruction and the associated pre-scheduled replay operations sequentially. If additional threads remain unserviced after execution of the instruction and the pre-scheduled replay operations, then additional replay operations are inserted via the replay loop, until all threads are serviced. One advantage of the disclosed technique is that divergent operations requiring one or more replay operations execute with reduced latency.

4. 发明申请

US20130159684A1 BATCHED REPLAYS OF DIVERGENT OPERATIONS 有权
标题翻译：批量操作的重复操作
公开(公告)号：US20130159684A1
公开(公告)日：2013-06-20
申请号：US13329066
申请日：2011-12-16
申请人： Michael Fetterman , Jack Hilaire Choquette , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Stewart glenn Carlton , Rajeshwaran Selvanesan , Douglas J. Hahn , Steven James Heinrich
发明人： Michael Fetterman , Jack Hilaire Choquette , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Stewart glenn Carlton , Rajeshwaran Selvanesan , Douglas J. Hahn , Steven James Heinrich
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3861
摘要： One embodiment of the present invention sets forth an optimized way to execute replay operations for divergent operations in a parallel processing subsystem. Specifically, the streaming multiprocessor (SM) includes a multistage pipeline configured to batch two or more replay operations for processing via replay loop. A logic element within the multistage pipeline detects whether the current pipeline stage is accessing a shared resource, such as loading data from a shared memory. If the threads are accessing data which are distributed across multiple cache lines, then the multistage pipeline batches two or more replay operations, where the replay operations are inserted into the pipeline back-to-back. Advantageously, divergent operations requiring two or more replay operations operate with reduced latency. Where memory access operations require transfer of more than two cache lines to service all threads, the number of clock cycles required to complete all replay operations is reduced.
摘要翻译：本发明的一个实施例阐述了在并行处理子系统中对发散操作执行重放操作的优化方法。具体地说，流式多处理器（SM）包括多级流水线，其被配置为批量两个或更多个重播操作以便经由重放循环进行处理。多级流水线内的逻辑元件检测当前流水线阶段是否正在访问共享资源，例如从共享内存加载数据。如果线程正在访问分布在多个高速缓存行中的数据，则多级管道批量执行两个或更多个重放操作，其中重放操作被背对背地插入到管道中。有利地，需要两次或更多次重放操作的发散操作以降低的等待时间运行。在存储器访问操作需要传送两条以上的高速缓存行以服务所有线程的情况下，完成所有重放操作所需的时钟周期数减少。

5. 发明授权

US09817668B2 Batched replays of divergent operations 有权
公开(公告)号：US09817668B2
公开(公告)日：2017-11-14
申请号：US13329066
申请日：2011-12-16
申请人： Michael Fetterman , Jack Hilaire Choquette , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Stewart Glenn Carlton , Rajeshwaran Selvanesan , Douglas J. Hahn , Steven James Heinrich
发明人： Michael Fetterman , Jack Hilaire Choquette , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Stewart Glenn Carlton , Rajeshwaran Selvanesan , Douglas J. Hahn , Steven James Heinrich
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3861
摘要： One embodiment of the present invention sets forth an approach for executing replay operations for divergent operations in a parallel processing subsystem. Specifically, the streaming multiprocessor (SM) includes a multistage pipeline configured to batch two or more replay operations for processing via replay loop. A logic element within the multistage pipeline detects whether the current pipeline stage is accessing a shared resource, such as loading data from a shared memory. If the threads are accessing data which are distributed across multiple cache lines, then the multistage pipeline batches two or more replay operations, where the replay operations are inserted into the pipeline back-to-back.

6. 发明申请

US20130145124A1 SYSTEM AND METHOD FOR PERFORMING SHAPED MEMORY ACCESS OPERATIONS 审中-公开
标题翻译：用于执行形状记忆访问操作的系统和方法
公开(公告)号：US20130145124A1
公开(公告)日：2013-06-06
申请号：US13312954
申请日：2011-12-06
申请人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
发明人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
IPC分类号： G06F9/30
CPC分类号： G06F15/167 , G06F9/3012 , G06F9/3455 , G06F9/383 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.
摘要翻译：本发明的一个实施例提出了提供从寄存器文件中检索操作数的有效方式的技术。具体地，指令分派单元接收一个或多个指令，每个指令包括一个或多个操作数。总的来说，操作数被组织成一个或多个操作数组，从中可以形成成形的访问。操作数从寄存器文件中检索并存储在收集器中。一旦所有操作数被读取并收集在收集器中，指令分派单元将指令和相应的操作数发送到流多处理器内的功能单元以供执行。本发明的一个优点是在没有资源冲突的情况下，在单个寄存器访问操作中从寄存器文件中检索多个操作数。通过形成有效地检索具有公认的存储器访问模式的操作数的形状访问来改进从寄存器文件中检索操作数的性能。

7. 发明授权

US10255228B2 System and method for performing shaped memory access operations 有权
公开(公告)号：US10255228B2
公开(公告)日：2019-04-09
申请号：US13312954
申请日：2011-12-06
申请人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
发明人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
IPC分类号： G06F9/30 , G06F15/167 , G06F9/38 , G06F9/345
摘要： One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.

8. 发明授权

US09830158B2 Speculative execution and rollback 有权
公开(公告)号：US09830158B2
公开(公告)日：2017-11-28
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.

9. 发明授权

US09798548B2 Methods and apparatus for scheduling instructions using pre-decode data 有权
公开(公告)号：US09798548B2
公开(公告)日：2017-10-24
申请号：US13333879
申请日：2011-12-21
申请人： Jack Hilaire Choquette , Robert J. Stoll , Olivier Giroux
发明人： Jack Hilaire Choquette , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/382
摘要： Systems and methods for scheduling instructions using pre-decode data corresponding to each instruction. In one embodiment, a multi-core processor includes a scheduling unit in each core for selecting instructions from two or more threads each scheduling cycle for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The pre-decode data is determined by a compiler and is extracted by the scheduling unit during runtime and used to control selection of threads for execution. The pre-decode data may specify a number of scheduling cycles to wait before scheduling the instruction. The pre-decode data may also specify a scheduling priority for the instruction. Once the scheduling unit selects an instruction to issue for execution, a decode unit fully decodes the instruction.

10. 发明申请

US20120110586A1 THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR 有权
标题翻译：用于并行螺纹加工器的螺纹组合调度器
公开(公告)号：US20120110586A1
公开(公告)日：2012-05-03
申请号：US13247819
申请日：2011-09-28
申请人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
发明人： Brett W. Coon , John R. Nickolls , John Erik Lindholm , Robert J. Stoll , Nicholas Wang , Jack Hilaire Choquette , Kathleen Elliott Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.
摘要翻译：并行线程处理器执行属于多个协作线程数组（CTA）的线程组。在并行线程处理器的每个周期，指令调度器在随后的周期中选择要发行的线程组以执行。指令调度器通过（i）识别可用线程组的池，（ii）识别具有最大资历值的CTA来选择要执行的线程组，以及（iii）选择具有最大信用值的线程组从具有最高资历价值的CTA内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式