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1. 发明申请

US20130166877A1 SHAPED REGISTER FILE READS 有权
标题翻译：形状寄存器文件读取
公开(公告)号：US20130166877A1
公开(公告)日：2013-06-27
申请号：US13335868
申请日：2011-12-22
申请人： Jack Hilaire CHOQUETTE , Michael FETTERMAN , Shirish GADRE , Xiaogang QIU , Omkar PARANJAPE , Anjana RAJENDRAN , Stewart Glenn CARLTON , Eric Lyell HILL , Rajeshwaran SELVANESAN , Douglas J. HAHN
发明人： Jack Hilaire CHOQUETTE , Michael FETTERMAN , Shirish GADRE , Xiaogang QIU , Omkar PARANJAPE , Anjana RAJENDRAN , Stewart Glenn CARLTON , Eric Lyell HILL , Rajeshwaran SELVANESAN , Douglas J. HAHN
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3012
摘要： One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers.
摘要翻译：本发明的一个实施例提出了一种用于执行包括一组N个寄存器的寄存器文件的形状访问的技术，其中N大于或等于2。该技术涉及对于包括在一组线程中的至少一个线程，接收从N个寄存器组中的每个寄存器访问第一数据量的请求，以及配置交叉开关以允许至少一个线程访问来自N个寄存器组中每个寄存器的第一个数据量。

2. 发明申请

US20130166882A1 METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTION DECODE 审中-公开
标题翻译：用于在没有指令解码的情况下安排指令的方法和装置
公开(公告)号：US20130166882A1
公开(公告)日：2013-06-27
申请号：US13335872
申请日：2011-12-22
申请人： Jack Hilaire CHOQUETTE , Robert J. STOLL , Olivier GIROUX , Michael FETTERMAN , Shirish GADRE , Robert Steven GLANVILLE , Alexandre JOLY
发明人： Jack Hilaire CHOQUETTE , Robert J. STOLL , Olivier GIROUX , Michael FETTERMAN , Shirish GADRE , Robert Steven GLANVILLE , Alexandre JOLY
IPC分类号： G06F9/30 , G06F9/38 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/382
摘要： Systems and methods for scheduling instructions without instruction decode. In one embodiment, a multi-core processor includes a scheduling unit in each core for scheduling instructions from two or more threads scheduled for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The scheduling unit includes a macro-scheduler unit for performing a priority sort of the two or more threads and a micro-scheduler arbiter for determining the highest order thread that is ready to execute. The macro-scheduler unit and the micro-scheduler arbiter use pre-decode data to implement the scheduling algorithm. The pre-decode data may be generated by decoding only a small portion of the instruction or received along with the instruction. Once the micro-scheduler arbiter has selected an instruction to dispatch to the execution unit, a decode unit fully decodes the instruction.
摘要翻译：用于调度指令而不进行指令解码的系统和方法。在一个实施例中，多核处理器包括每个核心中的调度单元，用于调度来自在该特定核心上执行的两个或更多个线程的指令。由于线程被安排在核心上执行，所以来自线程的指令被取入到缓冲器中而不被解码。调度单元包括用于执行两个或更多个线程的优先级排序的宏调度器单元和用于确定准备执行的最高阶线程的微调度器仲裁器。宏调度器单元和微调度器仲裁器使用预解码数据来实现调度算法。预解码数据可以仅通过解码指令的一小部分或与该指令一起被接收来产生。一旦微调度器仲裁器选择了向执行单元发送的指令，则解码单元对该指令进行完全解码。

3. 发明申请

US20130117541A1 SPECULATIVE EXECUTION AND ROLLBACK 有权
标题翻译：统一执行和滚动
公开(公告)号：US20130117541A1
公开(公告)日：2013-05-09
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.
摘要翻译：本发明的一个实施例提出了一种用于推测发出指令以允许处理流水线在其他指令的回滚期间继续处理一些指令的技术。调度器电路发出执行指令，假设几个周期后，当指令到达多线程执行单元时，指令之间的相关性将被解决，资源将可用，操作数数据将可用，而其他条件将不会阻止执行说明。当在特定线程组的指令的执行点处存在回滚条件时，指令不会分派给多线程执行单元。然而，由多线程执行单元执行由调度器电路发出的用于由不同线程组执行并且不存在回滚条件的其他指令。在回滚条件不再存在之后，重新发出导致回滚条件的指令。

4. 发明申请

US20130159628A1 METHODS AND APPARATUS FOR SOURCE OPERAND COLLECTOR CACHING 有权
标题翻译：来源操作收集器缓存的方法和装置
公开(公告)号：US20130159628A1
公开(公告)日：2013-06-20
申请号：US13326183
申请日：2011-12-14
申请人： Jack Hilaire CHOQUETTE , Manuel Olivier Gautho , John Erik Lindholm
发明人： Jack Hilaire CHOQUETTE , Manuel Olivier Gautho , John Erik Lindholm
IPC分类号： G06F12/08
CPC分类号： G06F9/3009 , G06F9/3012 , G06F9/3832
摘要： Methods and apparatus for source operand collector caching. In one embodiment, a processor includes a register file that may be coupled to storage elements (i.e., an operand collector) that provide inputs to the datapath of the processor core for executing an instruction. In order to reduce bandwidth between the register file and the operand collector, operands may be cached and reused in subsequent instructions. A scheduling unit maintains a cache table for monitoring which register values are currently stored in the operand collector. The scheduling unit may also configure the operand collector to select the particular storage elements that are coupled to the inputs to the datapath for a given instruction.
摘要翻译：源操作数采集器缓存的方法和装置。在一个实施例中，处理器包括可以耦合到存储元件（即，操作数收集器）的寄存器文件，其提供用于执行指令的处理器核的数据路径的输入。为了减少寄存器文件和操作数收集器之间的带宽，操作数可以在随后的指令中缓存并重新使用。调度单元维护高速缓存表，用于监视当前存储在操作数收集器中的寄存器值。调度单元还可以配置操作数收集器以选择耦合到给定指令的数据路径的输入的特定存储元件。

5. 发明申请

US20130166881A1 METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE DATA 有权
标题翻译：使用预编码数据调度指令的方法和装置
公开(公告)号：US20130166881A1
公开(公告)日：2013-06-27
申请号：US13333879
申请日：2011-12-21
申请人： Jack Hilaire CHOQUETTE , Robert J. Stoll , Olivier Giroux
发明人： Jack Hilaire CHOQUETTE , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/382
摘要： Systems and methods for scheduling instructions using pre-decode data corresponding to each instruction. In one embodiment, a multi-core processor includes a scheduling unit in each core for selecting instructions from two or more threads each scheduling cycle for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The pre-decode data is determined by a compiler and is extracted by the scheduling unit during runtime and used to control selection of threads for execution. The pre-decode data may specify a number of scheduling cycles to wait before scheduling the instruction. The pre-decode data may also specify a scheduling priority for the instruction. Once the scheduling unit selects an instruction to issue for execution, a decode unit fully decodes the instruction.
摘要翻译：用于使用对应于每个指令的预解码数据调度指令的系统和方法。在一个实施例中，多核处理器包括每个核心中的调度单元，用于从两个或更多个线程中选择用于在该特定核心上执行的调度周期的指令。由于线程被安排在核心上执行，所以来自线程的指令被取入到缓冲器中而不被解码。预解码数据由编译器确定，并且在运行时由调度单元提取并用于控制用于执行的线程的选择。预解码数据可以指定在调度指令之前等待的多个调度周期。预解码数据还可以指定该指令的调度优先级。一旦调度单元选择要执行的指令，则解码单元完全解码该指令。

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