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1. 发明授权

US09606808B2 Method and system for resolving thread divergences 有权
公开(公告)号：US09606808B2
公开(公告)日：2017-03-28
申请号：US13348544
申请日：2012-01-11
申请人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
发明人： Jack Choquette , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F9/3851
摘要： A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.

2. 发明申请

US20130179662A1 Method and System for Resolving Thread Divergences 有权
标题翻译：解决线程差异的方法和系统
公开(公告)号：US20130179662A1
公开(公告)日：2013-07-11
申请号：US13348544
申请日：2012-01-11
申请人： Jack CHOQUETTE , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
发明人： Jack CHOQUETTE , Xiaogang Qiu , Jeff Tuckey , Michael (Ming Yiu) Siu , Robert J. Stoll , Olivier Giroux
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
CPC分类号： G06F9/3887 , G06F9/3851
摘要： An address divergence unit detects divergence between threads in a thread group and then separates those threads into a subset of non-divergent threads and a subset of divergent threads. In one embodiment, the address divergence unit causes instructions associated with the subset of non-divergent threads to be issued for execution on a parallel processing unit, while causing the instructions associated with the subset of divergent threads to be re-fetched and re-issued for execution.
摘要翻译：地址发散单元检测线程组中的线程之间的差异，然后将这些线程分成非发散线程的子集和发散线程的子集。在一个实施例中，地址发散单元导致与非发散线程的子集相关联的指令用于在并行处理单元上执行，同时引起与分支线程的子集相关联的指令被重新获取并重新发布执行。

3. 发明授权

US09830158B2 Speculative execution and rollback 有权
公开(公告)号：US09830158B2
公开(公告)日：2017-11-28
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire Choquette , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.

4. 发明申请

US20130117541A1 SPECULATIVE EXECUTION AND ROLLBACK 有权
标题翻译：统一执行和滚动
公开(公告)号：US20130117541A1
公开(公告)日：2013-05-09
申请号：US13289643
申请日：2011-11-04
申请人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
发明人： Jack Hilaire CHOQUETTE , Olivier Giroux , Robert J. Stoll , Xiaogang Qiu
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists.
摘要翻译：本发明的一个实施例提出了一种用于推测发出指令以允许处理流水线在其他指令的回滚期间继续处理一些指令的技术。调度器电路发出执行指令，假设几个周期后，当指令到达多线程执行单元时，指令之间的相关性将被解决，资源将可用，操作数数据将可用，而其他条件将不会阻止执行说明。当在特定线程组的指令的执行点处存在回滚条件时，指令不会分派给多线程执行单元。然而，由多线程执行单元执行由调度器电路发出的用于由不同线程组执行并且不存在回滚条件的其他指令。在回滚条件不再存在之后，重新发出导致回滚条件的指令。

5. 发明授权

US08533435B2 Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict 有权
标题翻译：对分配给每个读取请求端口的操作数重新排序并发访问多银行寄存器文件以避免银行冲突
公开(公告)号：US08533435B2
公开(公告)日：2013-09-10
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

6. 发明申请

US20110072243A1 Unified Collector Structure for Multi-Bank Register File 有权
标题翻译：多银行登记册统一采集器结构
公开(公告)号：US20110072243A1
公开(公告)日：2011-03-24
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

7. 发明授权

US07484039B2 Method and apparatus for implementing a grid storage system 失效
标题翻译：用于实现电网存储系统的方法和装置
公开(公告)号：US07484039B2
公开(公告)日：2009-01-27
申请号：US11438411
申请日：2006-05-22
申请人： Xiaogang Qiu , Ningchuan Shen
发明人： Xiaogang Qiu , Ningchuan Shen
IPC分类号： G06F12/16
CPC分类号： H04L67/1095 , G06F3/0614 , G06F3/067 , G06F11/1076 , G06F11/1464 , G06F2201/84 , H04L67/1097 , H04L69/40
摘要： Embodiments of the present invention facilitate implementing external storage systems using commodity computer components to achieve high performance and reliability. An exemplary method facilitates dynamic repairing of disk failures for RAID1 storage coherently across a plurality of loosely coupled storage controller computers via message communications through network interfaces. An exemplary method facilitates snapshot function coherently across a plurality of loosely coupled storage controller nodes via message communications through network interfaces. An exemplary method facilitates to detect, tolerate, and repair temporary target device failures in a networked storage system. An exemplary target device may contain a plurality of disk devices, and a temporary target device failure may due to many reasons such as a network or software glitch.
摘要翻译：本发明的实施例有利于使用商品计算机组件实现外部存储系统以实现高性能和可靠性。一种示例性方法有助于通过经由网络接口的消息通信跨多个松散耦合的存储控制器计算机相干地进行RAID1存储的磁盘故障的动态修复。一种示例性方法通过经由网络接口的消息通信在多个松散耦合的存储控制器节点之间相干地实现快照功能。一种示例性方法有助于检测，容忍和修复网络存储系统中的临时目标设备故障。示例性目标设备可以包含多个磁盘设备，并且临时目标设备故障可能由于诸如网络或软件故障之类的许多原因。

8. 发明授权

US07188324B1 Assertion morphing in functional verification of integrated circuit design 有权
标题翻译：集成电路设计功能验证中的断言变形
公开(公告)号：US07188324B1
公开(公告)日：2007-03-06
申请号：US10893472
申请日：2004-07-16
申请人： Xiaogang Qiu , Si-En Chang
发明人： Xiaogang Qiu , Si-En Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318364
摘要： A method and apparatus provides a mechanism to transform or “morph” Formal verification method assertions so that an assertion defined in one Design Under Test (DUT) can be replicated, or derived, to propagate into other related DUTs. Using the method and apparatus of the present invention, individual DUTs can better leverage assertions defined independently in other DUT environments. This, in turn, provides for greater productivity and a faster, smoother verification process-using Formal and Assertion Based Verification methods.
摘要翻译：一种方法和装置提供了一种转换或“变形”形式验证方法断言的机制，使得可以复制或导出在一个被测设计（DUT）中定义的断言传播到其他相关的DUT。使用本发明的方法和装置，各个DUT可以更好地利用在其它DUT环境中独立定义的断言。反过来，使用正式和断言验证方法，提供更高的生产力和更快，更平滑的验证过程。

9. 发明申请

US20130145124A1 SYSTEM AND METHOD FOR PERFORMING SHAPED MEMORY ACCESS OPERATIONS 审中-公开
标题翻译：用于执行形状记忆访问操作的系统和方法
公开(公告)号：US20130145124A1
公开(公告)日：2013-06-06
申请号：US13312954
申请日：2011-12-06
申请人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
发明人： Xiaogang Qiu , Jack Hilaire Choquette , Manuel Olivier Gautho , Ming Y. (Michael) Siu
IPC分类号： G06F9/30
CPC分类号： G06F15/167 , G06F9/3012 , G06F9/3455 , G06F9/383 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns.
摘要翻译：本发明的一个实施例提出了提供从寄存器文件中检索操作数的有效方式的技术。具体地，指令分派单元接收一个或多个指令，每个指令包括一个或多个操作数。总的来说，操作数被组织成一个或多个操作数组，从中可以形成成形的访问。操作数从寄存器文件中检索并存储在收集器中。一旦所有操作数被读取并收集在收集器中，指令分派单元将指令和相应的操作数发送到流多处理器内的功能单元以供执行。本发明的一个优点是在没有资源冲突的情况下，在单个寄存器访问操作中从寄存器文件中检索多个操作数。通过形成有效地检索具有公认的存储器访问模式的操作数的形状访问来改进从寄存器文件中检索操作数的性能。

10. 发明授权

US08321761B1 ECC bits used as additional register file storage 有权
公开(公告)号：US08321761B1
公开(公告)日：2012-11-27
申请号：US12568552
申请日：2009-09-28
申请人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
发明人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
IPC分类号： G11C29/00
CPC分类号： G09G5/363 , G06F11/10 , G09G2330/12 , G09G2360/121 , G09G2360/125 , G11C2029/0411
摘要： A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.

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