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1. 发明申请

US20070247239A1 Phase modulator 审中-公开
标题翻译：相位调制器
公开(公告)号：US20070247239A1
公开(公告)日：2007-10-25
申请号：US11472447
申请日：2006-06-22
申请人： Jaako O. Maunuksela , Mikael Svard , Ari Vilander
发明人： Jaako O. Maunuksela , Mikael Svard , Ari Vilander
IPC分类号： H03B27/00
CPC分类号： H03C3/40
摘要： A modulator, comprising an input unit configured to receive a modulating signal, a control unit configured to provide a control signal on the basis of the modulating signal, an oscillating unit configured to provide a plurality of instances of at least two phase components of a carrier frequency signal, a phase selector configure to select, on the basis of the control signal, a combination of the phase component instances so that an output signal representing the information contents of the modulating signal is obtained, and a combiner configured to combine the selected phase component instances to form a modulated output signal.
摘要翻译：一种调制器，包括被配置为接收调制信号的输入单元，被配置为基于调制信号提供控制信号的控制单元，被配置为提供载波的至少两个相位分量的多个实例的振荡单元频率信号，相位选择器，其被配置为基于所述控制信号选择所述相位分量实例的组合，从而获得表示所述调制信号的信息内容的输出信号;以及组合器，被配置为将所选择的相位组件实例以形成调制输出信号。

2. 发明授权

US06922128B2 Method for forming a spiral inductor 有权
标题翻译：形成螺旋电感的方法
公开(公告)号：US06922128B2
公开(公告)日：2005-07-26
申请号：US10176101
申请日：2002-06-18
申请人： Ari Vilander , Mikael Svard , Lassi Hyvonen
发明人： Ari Vilander , Mikael Svard , Lassi Hyvonen
IPC分类号： H01F5/00 , H01F17/00 , H01F41/04 , H01L21/02 , H01L27/08
CPC分类号： H01L28/10 , H01F5/003 , H01F17/0006 , H01F41/041 , H01L27/08 , Y10T29/4902 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49069 , Y10T29/49073 , Y10T29/49078
摘要： A method for forming a spiral inductor (11) or component of a transformer, compatible with very large scale integrated processing, that achieves a higher Q value without occupying more space by splitting at least one turn (13 51) as two or more crisscrossing or interwoven smaller-width turns (13a 13b 52 53 54 55). The at least one turn (51) may, for example, be split into four turns paired up to provide two pairs of two turns, and the turns of each pair may then be interwoven or crisscrossed, and then the two pairs may also be interwoven or crisscrossed. The splitting of a turn into two or more smaller-width turns results in the current being divided among the smaller-width turns.
摘要翻译：一种用于形成与非常大规模的集成处理兼容的变压器的螺旋电感器（11）或分量的方法，其通过将至少一匝（13 51）分裂为两个或更多个交叉的方式实现更高的Q值而不占据更多的空间，交织较小的匝数（13 a 13 b 52 53 54 55）。至少一个转弯（51）可以例如被分成四个匝配对，以提供两对两匝，然后每对的匝可以交织或十字交叉，然后两对也可以交织或十字交叉。将转弯分为两个或更多个较小宽度的匝导致电流在较小宽度匝之间分配。

3. 发明申请

US20060290006A1 Semiconductor package 失效
标题翻译：半导体封装
公开(公告)号：US20060290006A1
公开(公告)日：2006-12-28
申请号：US11166493
申请日：2005-06-23
申请人： Mikael Svard , Nigel Martin
发明人： Mikael Svard , Nigel Martin
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L24/24 , H01L25/0655 , H01L25/18 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/00
摘要： A semiconductor package includes a combination die embedded in a base. The combination die includes a plurality of functional blocks, where the functional blocks are insulated from one another on the combination die. Each functional block has plural die connectors. The base includes insulating layers conductive layers and vias. Each conductive layer has parts removed to form a pattern. The base is provided with a plurality of external connectors. A conductive path, made from a part of at least one of the conductive layers and at least one of the vias, connects one of the die connectors to a respective one of the external connectors.
摘要翻译：半导体封装包括嵌入基座中的组合管芯。组合管芯包括多个功能块，其中功能块在组合管芯上彼此绝缘。每个功能块具有多个管芯连接器。基底包括绝缘层导电层和通孔。每个导电层具有去除部分以形成图案。基座设置有多个外部连接器。由至少一个导电层和至少一个通孔的一部分制成的导电路径将一个管芯连接器连接到相应的一个外部连接器。

4. 发明授权

US07327006B2 Semiconductor package 失效
标题翻译：半导体封装
公开(公告)号：US07327006B2
公开(公告)日：2008-02-05
申请号：US11166493
申请日：2005-06-23
申请人： Mikael Svard , Nigel Martin
发明人： Mikael Svard , Nigel Martin
IPC分类号： H01L31/00 , H01L21/44
CPC分类号： H01L23/5389 , H01L24/24 , H01L25/0655 , H01L25/18 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/00
摘要： A semiconductor package includes a combination die embedded in a base. The combination die includes a plurality of functional blocks, where the functional blocks are insulated from one another on the combination die. Each functional block has plural die connectors. The base includes insulating layers conductive layers and vias. Each conductive layer has parts removed to form a pattern. The base is provided with a plurality of external connectors. A conductive path, made from a part of at least one of the conductive layers and at least one of the vias, connects one of the die connectors to a respective one of the external connectors.
摘要翻译：半导体封装包括嵌入基座中的组合管芯。组合管芯包括多个功能块，其中功能块在组合管芯上彼此绝缘。每个功能块具有多个管芯连接器。基底包括绝缘层导电层和通孔。每个导电层具有去除部分以形成图案。基座设置有多个外部连接器。由至少一个导电层和至少一个通孔的一部分制成的导电路径将一个管芯连接器连接到相应的一个外部连接器。

5. 发明授权

US06784751B2 Method and apparatus providing resampling function in a modulus prescaler of a frequency source 有权
标题翻译：在频率源的模拟预分频器中提供重采样功能的方法和装置
公开(公告)号：US06784751B2
公开(公告)日：2004-08-31
申请号：US09955874
申请日：2001-09-18
申请人： Mika Salmi , Mikael Svard
发明人： Mika Salmi , Mikael Svard
IPC分类号： H03L700
CPC分类号： H03K21/40 , H03K21/08 , H03L7/193
摘要： A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.
摘要翻译：重采样技术用于降低噪声并提高预分频器电路输出中的信号质量（10）。使用由从预分频器的输入获得的信号计时的至少一个触发器（FF）（例如，D型FF18）来实现最后一个分频器级的输出的重新采样。这会降低或消除由预分频器的输出引起的边沿抖动引起的噪声，以及由预分频器产生的杂散信号的影响。这些教导可用于整数N个PLL和分数N个PLL，以及单个和可编程的双模或多模预分频器。使用这种技术，不需要增加预分频器分频器（12,14,16）的电流消耗，以减少预分频器噪声，从而节省电池供电和其他应用中的电流。

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