专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06201746B1 Test method for high speed memory devices in which limit conditions for the clock are defined 失效
标题翻译：定义时钟限制条件的高速存储器件的测试方法
公开(公告)号：US06201746B1
公开(公告)日：2001-03-13
申请号：US09107947
申请日：1998-06-30
申请人： Ja-hyun Koo , Jong-bok Tcho , Hyun-seop Shim , Jeong-ho Bang
发明人： Ja-hyun Koo , Jong-bok Tcho , Hyun-seop Shim , Jeong-ho Bang
IPC分类号： G11C700
CPC分类号： G11C29/14
摘要： When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.
摘要翻译：当使用具有比存储器件的操作速度更低的工作频率的测试仪测试高速存储器件时，需要测试仪信号的限制条件以防止测试仪和器件信号之间的干扰。本发明提供了移位和选通信号的限制条件。选通信号通过定义死区时间的传送延迟时间传送给比较器。移位信号控制设备到驱动器和比较器的数据路径。当选通信号在当前测试周期内时，读周期的移位信号必须与下一个写周期的WE /信号的激活时间相同或早于激活时间，并且写周期的移位信号必须同时或早于下一个读取周期的OE /信号的激活时间启动。当选通信号超出测试周期时，移位信号必须满足规定的最大和最小定时条件。

2. 发明授权

US07017428B2 Test kit for semiconductor package and method for testing semiconductor package using the same 失效
标题翻译：用于半导体封装的测试套件及使用其的半导体封装测试方法
公开(公告)号：US07017428B2
公开(公告)日：2006-03-28
申请号：US10728544
申请日：2003-12-04
申请人： Byoung-jun Min , Jeong-ho Bang , Hyun-seop Shim , Hyo-geun Chae
发明人： Byoung-jun Min , Jeong-ho Bang , Hyun-seop Shim , Hyo-geun Chae
IPC分类号： G01M19/00
CPC分类号： G01R31/2893 , G01R1/0483 , G01R31/2806
摘要： A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.
摘要翻译：提供了一种用于半导体封装的测试套件以及使用其的半导体封装测试方法。用于半导体封装的测试套件包括用于拾取和加载/卸载半导体封装的拾取和放置工具，具有封装导向器和插座导向器的头部组件以及位于头部组件下方的插座。套件导向器在包导向器开始操作之前执行用于正确操作包导向器的预对准功能。封装导向器对准半导体封装。

3. 发明授权

US07838790B2 Multifunctional handler system for electrical testing of semiconductor devices 有权
标题翻译：用于半导体器件电气测试的多功能处理器系统
公开(公告)号：US07838790B2
公开(公告)日：2010-11-23
申请号：US11983635
申请日：2007-11-09
申请人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
发明人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
IPC分类号： B07C5/34
CPC分类号： H01L21/67282 , G01R31/2867 , G01R31/2893 , H01L21/67271 , Y10S414/135
摘要： A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.
摘要翻译：提供了一种用于半导体器件的电测试的多功能处理器系统。多功能处理器系统包括：（1）半导体器件处理部分，包括包括缓冲器的加载单元，包括单独的标记机的分拣单元和卸载单元; （2）与半导体器件处理部分分离的半导体器件测试部分包括测试室，测试室被分离成两个或更多个测试空间，并且测试室的测试空间包括位于下部的第二室位置，位于第二室上方的第一室以及用于将第一和第二室彼此连接的管道; 和（3）独立地连接到半导体器件处理部分和半导体器件测试部分并且控制托盘信息，测试结果，标记信息和测试程序信息的主计算机。

4. 发明授权

US07554349B2 Handlers for testing semiconductor devices that are capable of maintaining stable temperature in test environments 有权
标题翻译：用于测试能够在测试环境中保持稳定温度的半导体器件的处理程序
公开(公告)号：US07554349B2
公开(公告)日：2009-06-30
申请号：US11727938
申请日：2007-03-29
申请人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
发明人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
IPC分类号： G01R31/02
CPC分类号： G01R31/2865 , G01R31/2862
摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.
摘要翻译：用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。测试室可以包括：测试板; 第一个房间第二个房间连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。

5. 发明申请

US20080110809A1 Multifunctional handler system for electrical testing of semiconductor devices 有权
标题翻译：用于半导体器件电气测试的多功能处理器系统
公开(公告)号：US20080110809A1
公开(公告)日：2008-05-15
申请号：US11983635
申请日：2007-11-09
申请人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
发明人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
IPC分类号： G01R31/28 , B07C5/344 , G01R31/319 , B65G65/02
CPC分类号： H01L21/67282 , G01R31/2867 , G01R31/2893 , H01L21/67271 , Y10S414/135
摘要： A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.
摘要翻译：提供了一种用于半导体器件的电测试的多功能处理器系统。多功能处理器系统包括：（1）半导体器件处理部分，包括包括缓冲器的加载单元，包括单独的标记机的分拣单元和卸载单元; （2）与半导体器件处理部分分离的半导体器件测试部分包括测试室，测试室被分离成两个或更多个测试空间，并且测试室的测试空间包括位于下部的第二室位置，位于第二室上方的第一室以及用于将第一和第二室彼此连接的管道; 和（3）独立地连接到半导体器件处理部分和半导体器件测试部分并且控制托盘信息，测试结果，标记信息和测试程序信息的主计算机。

6. 发明授权

US5959915A Test method of integrated circuit devices by using a dual edge clock technique 失效
标题翻译：使用双边沿时钟技术的集成电路器件的测试方法
公开(公告)号：US5959915A
公开(公告)日：1999-09-28
申请号：US107093
申请日：1998-06-29
申请人： Hyuk Kwon , Dong-wook Kim , Keun-won Cho , Hyun-seop Shim
发明人： Hyuk Kwon , Dong-wook Kim , Keun-won Cho , Hyun-seop Shim
IPC分类号： G01R31/28 , G01R31/319 , G06F11/22 , G11C11/401 , G11C11/407 , G11C11/413 , G11C29/56 , G11C7/00
CPC分类号： G01R31/31922
摘要： A test method can test high speed synchronous memory devices by using a tester having a minimum rate and a minimum clock cycle slower than operating speed of the devices to be tested. The test method transforms a pulse signal generated by the tester to be transformed into a clock signal having a frequency higher than the minimum rate, a test cycle of the test equipment then being determined based on a cycle time of the pulse signal, the operating cycle of the IC devices being determined based on a cycle time of the clock signal, and an input setup time and an input hold time of control signals which are supplied from the tester to the devices are separately measured for every two or more operating cycles of the IC devices.
摘要翻译：一种测试方法可以通过使用测试仪测试高速同步存储器件，该测试仪的最小速率和最小时钟周期要慢于要测试的器件的工作速度。测试方法将由测试仪生成的脉冲信号变换为频率高于最小速率的时钟信号，然后根据脉冲信号的周期时间确定测试周期，操作周期基于时钟信号的周期时间来确定IC器件，并且从测试器向器件提供的控制信号的输入建立时间和输入保持时间分别测量为每两个或更多个操作周期 IC器件。

7. 发明申请

US20070236235A1 Handlers for testing semiconductor devices that are capable of maintaining stable temperature in test environments 有权
标题翻译：用于测试能够在测试环境中保持稳定温度的半导体器件的处理程序
公开(公告)号：US20070236235A1
公开(公告)日：2007-10-11
申请号：US11727938
申请日：2007-03-29
申请人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
发明人： Seong-goo Kang , Jun-ho Lee , Ki-sang Kang , Hyun-seop Shim , Do-young Kam , Jae-il Lee , Ju-il Kang
IPC分类号： G01R31/02
CPC分类号： G01R31/2865 , G01R31/2862
摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.
摘要翻译：用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。测试室可以包括：测试板; 第一个房间第二个房间连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式