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    • 6. 发明申请
    • Reference voltage generator circuit
    • 参考电压发生器电路
    • US20060006927A1
    • 2006-01-12
    • US11174927
    • 2005-07-05
    • Akira Nakada
    • Akira Nakada
    • G05F1/10
    • G05F3/30
    • A reference voltage generator circuit includes: a band gap circuit that outputs a predetermined voltage to an output terminal; a plurality of current mirror circuits, a gate electrode of at least one of which being coupled with one current path, and a gate electrode of at least another one of which being coupled with an other current path, and which are further coupled with the band gap circuit so as to supply an output current to the output terminal corresponding to a current flowing in either the one or the other current path; and a control unit that detects an output voltage of the output terminal of the band gap circuit and that controls a current flowing in at least the one or the other current path corresponding to the detected output voltage.
    • 参考电压发生器电路包括:向输出端子输出预定电压的带隙电路; 多个电流镜电路,其中至少一个与一个电流通路耦合的栅电极和至少另一个栅电极与另一电流路径耦合,并且还与带 以向与所述一个或另一个电流路径中流动的电流相对应的输出端提供输出电流; 以及控制单元,其检测所述带隙电路的输出端子的输出电压,并且控制至少一个或另一个电流通路中流动的电流,所述电流路径对应于所检测的输出电压。
    • 10. 发明授权
    • System and method for resetting a microprocessor system
    • 用于复位微处理器系统的系统和方法
    • US5297287A
    • 1994-03-22
    • US844494
    • 1992-03-02
    • Yoshiyuki MiyayamaAkira NakadaJun NakamuraShoichiro Kasahara
    • Yoshiyuki MiyayamaAkira NakadaJun NakamuraShoichiro Kasahara
    • G06F1/24
    • G06F1/24
    • The present invention provides a reset circuit with two different threshold input voltages. The reset circuit of the present invention is located within a processor, and is designed to control the reset functions of both the processor and the chips located peripheral to the processor. The reset circuit includes a first buffer with a first threshold voltage level. The input of the first buffer is connected to a reset signal and the output of the first buffer is connected to control the reset function of at least one chip that is peripheral to the processor. A second buffer is provided with a second threshold voltage level that is higher than the first threshold voltage level. The input of the second buffer is connected to the reset signal and the output of the second buffer is connected to control the reset function of the processor. The reset circuit guarantees that the processor is reset after the peripheral chips subsequent to power up.
    • 本发明提供具有两个不同阈值输入电压的复位电路。 本发明的复位电路位于处理器内,并被设计成控制处理器和位于处理器周边的芯片的复位功能。 复位电路包括具有第一阈值电压电平的第一缓冲器。 第一缓冲器的输入连接到复位信号,并且第一缓冲器的输出被连接以控制处理器外围的至少一个芯片的复位功能。 第二缓冲器被提供有高于第一阈值电压电平的第二阈值电压电平。 第二缓冲器的输入连接到复位信号,第二缓冲器的输出被连接以控制处理器的复位功能。 复位电路保证处理器在上电后的外围芯片之后复位。