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    • 3. 发明授权
    • Processor controller, processor control method, storage medium, and external controller
    • 处理器控制器,处理器控制方式,存储介质和外部控制器
    • US08060778B2
    • 2011-11-15
    • US12198927
    • 2008-08-27
    • Michiharu Hara
    • Michiharu Hara
    • G06F11/00
    • G06F11/0793G06F11/0724G06F12/0804
    • A processor having a plurality of hardware resources can perform separate controls within a proper range according to the dependent relations of hardware resources troubled. In case a notification is made of the failure of the hardware resources constituting the processor, a processor control method decides the range of the hardware resources, which cannot be used because of that failure, as a failure range, on the basis of the dependencies of the individual hardware resources predetermined, and stops the use of the hardware resources of the failure range on the basis of that decision result. When the use of the hardware resources indicated by the failure range is stopped, the hardware is not stopped before a predetermined operation is performed not to affect the instruction processing procedure outside of the failure range.
    • 具有多个硬件资源的处理器可以根据硬盘资源的依赖关系在适当的范围内执行单独的控制。 在通知构成处理器的硬件资源的故障的情况下,处理器控制方法根据故障范围将由于该故障而不能使用的硬件资源的范围确定为故障范围, 预先确定各个硬件资源,并基于该判定结果停止对故障范围的硬件资源的使用。 当停止使用由故障范围指示的硬件资源时,在执行预定操作之前硬件不停止,而不影响故障范围之外的指令处理过程。
    • 4. 发明授权
    • Instruction control apparatus for loading plurality of instructions into execution stage
    • 用于将多个指令加载到执行阶段的指令控制装置
    • US06530013B1
    • 2003-03-04
    • US09461422
    • 1999-12-16
    • Michiharu HaraAiichiro Inoue
    • Michiharu HaraAiichiro Inoue
    • G06F9312
    • G06F9/3816G06F9/30149
    • In an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer, the amount of circuitry is reduced while achieving high speed processing. The instruction control apparatus includes a selection circuit and a pointer that points to the beginning of the next instruction word, within the instruction sequence fetched in a holding means, to be loaded into an execution stage. The selection circuit first selects a portion of the instruction sequence, starting from the beginning pointed to by the pointer and extending until reaching a maximum length of instructions that can be loaded into the execution stage, then simultaneously examines the lengths of instructions contained in the selected portion on the basis of a minimum instruction length unit, and selects the plurality of instructions to be loaded into the execution stage, based on the combination of the instruction lengths. One or more instructions thus selected are held in a plurality of loading ports.
    • 在能够从指令缓冲器同时选择不同指令长度的多个指令的指令控制装置中,在实现高速处理的同时减少电路的数量。 指令控制装置包括选择电路和指向下一个指令字的起始位置的指针,该指针在保持装置中取出的指令序列中被加载到执行阶段。 选择电路首先从指针指向的开始首先选择指令序列的一部分,并延伸直到达到可以加载到执行阶段的指令的最大长度,然后同时检查包含在所选择的指令中的指令长度 并根据指令长度的组合选择要加载到执行阶段的多个指令。 如此选择的一个或多个指令被保存在多个加载端口中。