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1. 发明授权

US06637016B1 Assignment of cell coordinates 有权
标题翻译：分配单元坐标
公开(公告)号：US06637016B1
公开(公告)日：2003-10-21
申请号：US09841824
申请日：2001-04-25
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.
摘要翻译：一种用于选择性地将专用集成电路的单元放置在衬底表面上的方法，包括以下步骤：限定覆盖衬底表面的栅格，将单元分配给栅格以提供单元相对于栅格的旧x和y坐标，通过功能对细胞进行分组以在网格内提供功能区域，确定网格内所有功能区域中基底表面的密度图，确定基底表面上的网格相对于密度图的自由空间，并将新的单元分配给衬底表面上的栅格的自由空间以提供专用集成电路。该方法的使用提供了具有最小的信元拥塞或重叠的集成电路的改进布局。

2. 发明授权

US06470487B1 Parallelization of resynthesis 有权
标题翻译：再合成平行化
公开(公告)号：US06470487B1
公开(公告)日：2002-10-22
申请号：US09842350
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated. Upon inactivation of all of the ordinal threads, a return is made to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.
摘要翻译：一种使用并行处理模式重新合成集成电路的设计的方法。通过激活主线程并锁定与主线程相关联的信号量来输入单个处理模式。集成电路的设计使用主线重新合成。识别以并行处理模式完成的任务。与主线程相关联的信号量被解锁，并且停止单处理模式的操作。通过解锁与每个顺序线程相关联的信号量激活有序线程。通过将任务分配给顺序线程和主线程，并行处理任务。在通过其中一个顺序线程完成一个分配的任务之后，确定是否还有一个额外的任务被分配。在附加任务保留的情况下，附加任务被分配给完成的一个序数线程。在附加任务不存在的情况下，完成的一个顺序线程将被禁用。在所有顺序线程失效后，返回到单个处理模式，顺序线程保持不活动，除非主线程在并行处理模式下识别要完成的更多任务。

3. 发明授权

US06701493B2 Floor plan tester for integrated circuit design 失效
标题翻译：集成电路设计平面图测试仪
公开(公告)号：US06701493B2
公开(公告)日：2004-03-02
申请号：US10109113
申请日：2002-03-27
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.
摘要翻译：在再合成之前测试集成电路的平面图的方法包括尝试构造在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有不可达的销; 并且如果构造最小惩罚路径，则尝试构建在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有瓶颈。

4. 发明授权

US06629304B1 Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells 有权
标题翻译：电池放置在集成电路芯片中，以去除单元重叠，行溢出和双高度单元的最佳放置
公开(公告)号：US06629304B1
公开(公告)日：2003-09-30
申请号：US09955698
申请日：2001-09-19
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu , Ivan Pavisic
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu , Ivan Pavisic
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.
摘要翻译：在集成电路芯片的单元放置过程期间，从行中移除单元格重叠。行被划分为子行，使得每个子行中的单元具有公共特征向量。通过移动溢出的行的单元或交换两个单元，其中至少一个在溢出的子行中，从每个子行移除单元溢出。基于所计算的运动损失，双高度单元的半单元以合适的行对移动到单元位置。完成运动以对准半细胞并最小化处罚。在优选实施例中，该过程由计算机在计算机程序的控制下执行。

5. 发明授权

US06553551B1 Timing recomputation 有权
标题翻译：定时重新计算
公开(公告)号：US06553551B1
公开(公告)日：2003-04-22
申请号：US09841825
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5031
摘要： A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.
摘要翻译：一种计算集成电路设计的路径的定时边缘的定时延迟的方法。根据该方法，识别路径内的所有引脚，并且识别由路径内的引脚限定的所有定时边缘。路径中的所有引脚都是路径中时间边缘之一的引导引脚。对于路径内的每个给定的引脚，列出了沿着路径中的连续的时序边缘序列从给定引脚上游的多个引脚。基于给定引脚的列表号码，给定引脚分配计算等级。定时边缘根据路径中每个时序边沿的引导引脚的计算等级进行排序，以产生定时边缘的有序列表。根据定时边缘的有序列表计算路径的定时边缘的定时延迟。

6. 发明授权

US06550044B1 Method in integrating clock tree synthesis and timing optimization for an integrated circuit design 有权
标题翻译：集成电路设计的时钟树合成和时序优化集成方法
公开(公告)号：US06550044B1
公开(公告)日：2003-04-15
申请号：US09885589
申请日：2001-06-19
申请人： Ivan Pavisic , Aiguo Lu , Andrej A. Zolotykh , Elyar E. Gasanov
发明人： Ivan Pavisic , Aiguo Lu , Andrej A. Zolotykh , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
摘要翻译：公开了一种合成用于集成电路设计的时钟树的方法，其包括以下步骤：为集成电路设计构建初始平衡时钟树; 计算初始时钟树中每个时钟驱动单元的时钟到达时间; 从针对每个时钟驱动单元计算的时钟到达时间执行时序分析; 并且与定时分析同时执行偏斜优化，以校正由定时分析发现的定时违规。

7. 发明授权

US06810515B2 Process of restructuring logics in ICs for setup and hold time optimization 失效
标题翻译：在IC中重组逻辑的过程进行设置和保持时间优化
公开(公告)号：US06810515B2
公开(公告)日：2004-10-26
申请号：US10254380
申请日：2002-09-25
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh , Elyar E. Gasanov
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations. Cost functions are calculated for each pin based on setup and hold time violations, and are selectively applied to the resynthesis steps.
摘要翻译：优化建立和保持时间冲突的过程，包括耦合到集成电路的引脚的数据和时钟逻辑的合成，以优化建立时间违规，以及重新合并耦合到集成电路引脚的数据和时钟逻辑，以优化保持时间违规。通过重新合成具有建立时间违规的每个引脚的时钟逻辑来优化建立时间违规，优化建立时间违规，然后重新合成具有建立时间违规的每个引脚的数据逻辑，以优化建立时间违规，以及然后重新合成具有设置时间违规的每个引脚的时钟逻辑，以优化设置时间违例。然后通过重新合并数据逻辑来优化保持时间违规，然后重新合成时钟逻辑以优化保持时间违规来优化保持时间违规。根据建立和保持时间违规计算每个引脚的成本函数，并选择性地应用于再合成步骤。

8. 发明授权

US06868536B2 Method to find boolean function symmetries 失效
标题翻译：查找布尔函数对称性的方法
公开(公告)号：US06868536B2
公开(公告)日：2005-03-15
申请号：US10299564
申请日：2002-11-19
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.
摘要翻译：本发明涉及一种查找布尔对称性的系统和方法。在本发明的方面，方法，系统和计算机可读介质为任何布尔函数构造对称树。描述布尔函数的交换变量组的数据结构称为布尔函数的对称树。

9. 发明授权

US06550045B1 Changing clock delays in an integrated circuit for skew optimization 有权
标题翻译：改变用于偏移优化的集成电路中的时钟延迟
公开(公告)号：US06550045B1
公开(公告)日：2003-04-15
申请号：US09991574
申请日：2001-11-20
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykj , Elyar E. Gasanov
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykj , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.
摘要翻译：时钟延迟在ASIC的时钟网络中发生变化。通过重构时钟域来平衡域中的时钟延迟并通过均衡具有时间路径的组的几个域的时钟延迟来实现全局偏移优化。使用影响相应域的所有叶片的缓冲器链和延迟时间相等的附加延迟系数来均衡时钟延迟。基于数据和时钟逻辑，通过重组组中的缓冲区来为每个组改变时钟插入延迟，以优化路径。局部偏移优化是通过使用启发式算法重构时钟域并重新排序域缓冲来实现的。计算机程序使得处理器能够执行这些处理。

10. 发明授权

US06543032B1 Method and apparatus for local resynthesis of logic trees with multiple cost functions 有权
标题翻译：具有多个成本函数的逻辑树的局部再合成方法和装置
公开(公告)号：US06543032B1
公开(公告)日：2003-04-01
申请号：US09678479
申请日：2000-10-02
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Alexander S. Podkolzin , Valery B. Kudryavtsev
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Alexander S. Podkolzin , Valery B. Kudryavtsev
IPC分类号： G06F1715
CPC分类号： G06F17/505
摘要： Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.
摘要翻译：提供了用于优化集成电路设计的系统和技术，其中在集成电路设计中识别关键区域，并且在临界区域中应用多个备选标识，以获得相应的多个结果。然后，替代表示被识别为多个结果中的代表性表示，根据该结果，突发时间和定时中的至少一个被改进，并且基于指定的优先级来选择替代表示中的最佳替代表示来替换到临界区，所述优先级包括：（i ）选择基于减少违约时间; （ii）从基于时间改进保留细胞区域的替代表示中进行选择; 和（iii）如果所有替代表示增加单元格区域，则基于对时间递减和面积增量之间的关系的评估进行选择。

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