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1. 发明授权

US07408421B2 Determining thermal absorption using ring oscillator 有权
标题翻译：使用环形振荡器确定热吸收
公开(公告)号：US07408421B2
公开(公告)日：2008-08-05
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要由非硅化多晶硅电阻器的电阻变化而变化。非硅化多晶硅电阻器的尺寸足够大，使得非硅化多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。非硅化多晶硅电阻的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

2. 发明申请

US20080007354A1 DETERMINING THERMAL ABSORPTION USING RING OSCILLATOR 有权
标题翻译：使用振荡器确定热吸收
公开(公告)号：US20080007354A1
公开(公告)日：2008-01-10
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including an un-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the un-silicided poly-silicon resistor. The dimensions of the un-silicided poly-silicon resistor are large enough so that the resistance of the un-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the un-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要随着未硅化多晶硅电阻器的电阻的变化而变化。未硅化多晶硅电阻器的尺寸足够大，使得未硅化的多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。未硅化的多晶硅电阻器的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

3. 发明授权

US07396694B2 Structure for monitoring semiconductor polysilicon gate profile 有权
标题翻译：用于监测半导体多晶硅栅极分布的结构
公开(公告)号：US07396694B2
公开(公告)日：2008-07-08
申请号：US11539231
申请日：2006-10-06
申请人： Ishtiaq Ahsan , Edward P. Maciejewski
发明人： Ishtiaq Ahsan , Edward P. Maciejewski
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.
摘要翻译：通过测试结构（1）测量相同多晶硅线（2）的横截面积的底部宽度和平均宽度与两个测量值相关联的测试结构来增强多晶硅线的轮廓漂移的检测，并且（3）比较这与以前的相同多晶硅线的横截面积的底宽与平均宽度的相关性的相关性。

4. 发明授权

US07135346B2 Structure for monitoring semiconductor polysilicon gate profile 失效
公开(公告)号：US07135346B2
公开(公告)日：2006-11-14
申请号：US10901870
申请日：2004-07-29
申请人： Ishtiaq Ahsan , Edward P. Maciejewski
发明人： Ishtiaq Ahsan , Edward P. Maciejewski
IPC分类号： H01L21/26 , H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.

5. 发明授权

US07719005B2 Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process 失效
标题翻译：用于监测和表征半导体制造工艺中图案密度依赖于热吸收的结构和方法
公开(公告)号：US07719005B2
公开(公告)日：2010-05-18
申请号：US11672059
申请日：2007-02-07
申请人： Ishtiaq Ahsan , Oleg Gluschenkov
发明人： Ishtiaq Ahsan , Oleg Gluschenkov
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , H01L22/12 , H01L22/20
摘要： According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.
摘要翻译：根据本发明，公开了一种使用该装置来表征和监测图案密度对半导体热吸收的依赖性的热检测装置和方法。一个或多个装置可以设置在测试晶片的管芯上。热检测装置包括具有基本上位于硅衬底的中心的测试结构的硅衬底。具有各种构造的多晶硅，硅和氧化物的框形结构在硅衬底上形成并置布置。对测试晶片进行快速热处理，并且测量至少一个测试结构的电阻，并将测量的至少一个测试结构的电阻列表成至少一个管芯的热吸收值。

6. 发明申请

US20100301331A1 BODY CONTACT STRUCTURE FOR IN-LINE VOLTAGE CONTRAST DETECTION OF PFET SILICIDE ENCROACHMENT 失效
标题翻译：用于在线电压对比检测PFET硅胶加密的身体接触结构
公开(公告)号：US20100301331A1
公开(公告)日：2010-12-02
申请号：US12471723
申请日：2009-05-26
申请人： Oliver D. Patterson , Ishtiaq Ahsan
发明人： Oliver D. Patterson , Ishtiaq Ahsan
IPC分类号： H01L27/06
CPC分类号： H01L22/34
摘要： Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures use body contacts, and the PFET components (source, drain, body, and gate) are either grounded, or floating, depending on the configuration. Some embodiments of the present invention also enable the use of positive mode conditions with PFET test structures, which provides for improved contrast in the VC images, improving the effectiveness of the defect detection achieved with VC imaging.
摘要翻译：公开了用于PFET硅化物侵蚀缺陷的在线电压对比度检测的测试结构。本发明的实施例提供了用于使用VC成像技术检测侵入缺陷的改进的PFET测试结构。测试结构使用主体触点，并且PFET组件（源，漏极，主体和门）根据配置而接地或浮动。本发明的一些实施例还使得能够利用PFET测试结构使用正模式条件，其提供VC图像中改善的对比度，从而提高用VC成像实现的缺陷检测的有效性。

7. 发明申请

US20090073796A1 MEMORY ARRAY PERIPHERAL STRUCTURES AND USE 失效
标题翻译：记忆阵列外围结构和使用
公开(公告)号：US20090073796A1
公开(公告)日：2009-03-19
申请号：US11856964
申请日：2007-09-18
申请人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
发明人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/02 , G11C5/06 , G11C29/006 , G11C29/24 , G11C29/48 , G11C29/808 , G11C29/816 , G11C29/838
摘要： A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.
摘要翻译：一种使用设置在作为测试结构的一组主存储器单元周围的环的光刻虚拟存储单元的方法和作为冗余存储单元的方法。还有具有多次使用的虚拟存储器单元的存储器阵列的电路和结构。

8. 发明授权

US07119545B2 Capacitive monitors for detecting metal extrusion during electromigration 失效
标题翻译：用于在电迁移期间检测金属挤压的电容式监视器
公开(公告)号：US07119545B2
公开(公告)日：2006-10-10
申请号：US10711641
申请日：2004-09-29
申请人： Ishtiaq Ahsan , Ronald Gene Filippi , Roy Charles Iggulden , Edward William Kiewra , Ping-Chuan Wang
发明人： Ishtiaq Ahsan , Ronald Gene Filippi , Roy Charles Iggulden , Edward William Kiewra , Ping-Chuan Wang
IPC分类号： G01R31/08 , G01R27/26
CPC分类号： H01L22/34 , G01R31/2858 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.
摘要翻译：一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。

9. 发明申请

US20060024853A1 Structure for monitoring semiconductor polysilicon gate profile 失效
标题翻译：用于监测半导体多晶硅栅极分布的结构
公开(公告)号：US20060024853A1
公开(公告)日：2006-02-02
申请号：US10901870
申请日：2004-07-29
申请人： Ishtiaq Ahsan , Edward Maciejewski
发明人： Ishtiaq Ahsan , Edward Maciejewski
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.
摘要翻译：通过测试结构（1）测量相同多晶硅线（2）的横截面积的底部宽度和平均宽度与两个测量值相关联的测试结构来增强多晶硅线的轮廓漂移的检测，并且（3）比较这与以前的相同多晶硅线的横截面积的底宽与平均宽度的相关性的相关性。

10. 发明授权

US08610451B2 Post silicide testing for replacement high-k metal gate technologies 有权
标题翻译：后置硅化物测试替代高k金属栅极技术
公开(公告)号：US08610451B2
公开(公告)日：2013-12-17
申请号：US12946875
申请日：2010-11-16
申请人： Ishtiaq Ahsan , David M. Fried , Lidor Goren , Jiun-Hsin Liao
发明人： Ishtiaq Ahsan , David M. Fried , Lidor Goren , Jiun-Hsin Liao
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2621
摘要： A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.
摘要翻译：用于测试IC器件中的晶体管栅极结构的测试结构包括形成在IC器件的有效区域上的一个或多个探针焊盘; 一个或多个第一导电线形成在所述IC器件的有源区，与所述一个或多个探针焊盘电接触; 形成在所述IC器件的栅极导体级的一个或多个第二导线，与所述一个或多个第一导线电接触; 以及要与所述一个或多个第二导线电接触测试的栅电极结构; 其中所述一个或多个第二导电线与所述一个或多个第一导电线之间的电接触由设置在所述一个或多个第二导电线与所述一个或多个第一导电线之间的栅极电介质材料的局部介电击穿来促进。

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