专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07277346B1 Method and system for hard failure repairs in the field 有权
标题翻译：在现场进行硬故障维修的方法和系统
公开(公告)号：US07277346B1
公开(公告)日：2007-10-02
申请号：US11012877
申请日：2004-12-14
申请人： Irfan Rahim , Peter J. McElheny , Eric Choong-Yin Chang
发明人： Irfan Rahim , Peter J. McElheny , Eric Choong-Yin Chang
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/14 , G11C29/42 , G11C29/4401 , G11C2029/0409
摘要： A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and repairing the failure by activating a redundancy circuit in the packaged integrated circuit system and deactivating a defective circuit associated with the failure. The process for repairing the failure includes applying a repair voltage to a polysilicon fuse to change a conductivity state of the polysilicon fuse from a first state to a second state. In another embodiment, the polysilicon fuse is replaced by a metal fuse, an anti-fuse, or a non-volatile random access memory.
摘要翻译：提供了一种用于修复封装集成电路系统的故障的半导体系统和方法。该方法包括在打包的集成电路系统被封装之后检测与封装的集成电路系统相关联的故障，以及通过激活封装的集成电路系统中的冗余电路来修复故障，并且去激活与故障相关的故障电路。修复故障的过程包括将修复电压施加到多晶硅熔丝以将多晶硅熔丝的导电状态从第一状态改变到第二状态。在另一个实施例中，多晶硅熔丝由金属熔断器，反熔丝或非易失性随机存取存储器代替。

2. 发明授权

US07902611B1 Integrated circuit well isolation structures 有权
标题翻译：集成电路阱隔离结构
公开(公告)号：US07902611B1
公开(公告)日：2011-03-08
申请号：US11998016
申请日：2007-11-27
申请人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
发明人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
IPC分类号： H01L21/70 , H01L23/52 , H01L29/00
CPC分类号： H01L27/0928 , H01L21/76224 , H01L21/765 , H01L21/823878 , H01L21/823892
摘要： An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.
摘要翻译：集成电路设置有可独立偏置的晶体管本体区域。一些物体可能被向前偏置，以降低阈值电压并增加晶体管切换速度。一些物体可能被反向体偏置以增加阈值电压并减小漏电流。集成电路可以形成在硅衬底上。可以在硅衬底中形成体偏置隔离结构以将体彼此隔离。体偏置隔离结构可以由浅沟槽隔离沟槽形成。可以使用离子注入在沟槽的底部形成掺杂区域。氧化物可用于填充掺杂区域上方的沟槽。可以在身体区域下方形成深井。深阱可以接触形成在沟槽底部的掺杂区域。

3. 发明授权

US07812408B1 Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers 有权
标题翻译：具有增强的栅耗尽层的金属氧化物半导体晶体管的集成电路
公开(公告)号：US07812408B1
公开(公告)日：2010-10-12
申请号：US11975010
申请日：2007-10-16
申请人： Albert Ratnakumar , Peter J. McElheny
发明人： Albert Ratnakumar , Peter J. McElheny
IPC分类号： H01L27/088
CPC分类号： H01L21/82345 , H01L21/823462 , H01L27/088
摘要： An integrated circuit is provided with groups of transistors that handle different maximum voltage levels. The transistors may be metal-oxide-semiconductor transistors having body, source, drain, and gate terminals. The gate of each transistor may have a gate insulator and a gate conductor. The gate conductor may be formed from a semiconductor such as polysilicon. Adjacent to the gate insulator, the polysilicon gate conductor may have a depletion layer. The depletion layer may have a thickness that is related to the doping level in the polysilicon gate conductor. By reducing the doping level in the polysilicon gates of some of the transistors, the equivalent oxide thickness of those transistors is increased, thereby enhancing their ability to withstand elevated voltages without experiencing gate oxide breakdown due to hot carrier injection effects.
摘要翻译：集成电路设置有处理不同最大电压电平的晶体管组。晶体管可以是具有主体，源极，漏极和栅极端子的金属氧化物半导体晶体管。每个晶体管的栅极可以具有栅极绝缘体和栅极导体。栅极导体可以由诸如多晶硅的半导体形成。与栅极绝缘体相邻，多晶硅栅极导体可以具有耗尽层。耗尽层可以具有与多晶硅栅极导体中的掺杂水平相关的厚度。通过降低一些晶体管的多晶硅栅极中的掺杂水平，这些晶体管的等效氧化物厚度增加，从而增强了其承受高电压的能力，而不会由于热载流子注入效应而经历栅极氧化物击穿。

4. 发明授权

US06187634B1 Process for making an EEPROM active area castling 失效
标题翻译：制造EEPROM活动区域铸造的过程
公开(公告)号：US06187634B1
公开(公告)日：2001-02-13
申请号：US09045737
申请日：1998-03-19
申请人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
发明人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
IPC分类号： H01L21336
CPC分类号： H01L27/11519 , H01L27/0203 , Y10S438/942
摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.
摘要翻译：提供了一个“castled”活动区域面罩。壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

5. 发明授权

US06038171A Field emission erasable programmable read-only memory 失效
标题翻译：场发射可擦除可编程只读存储器
公开(公告)号：US06038171A
公开(公告)日：2000-03-14
申请号：US953849
申请日：1997-10-15
申请人： Peter J. McElheny
发明人： Peter J. McElheny
IPC分类号： G11C16/04 , G11C16/14 , H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： G11C16/0408 , G11C16/14 , H01L21/28273 , H01L29/42328 , H01L29/7881
摘要： Disclosed is a field-emission erasable programmable read-only memory cell which includes one or more field-emission tips on one or more layers of the cell. The cell is programmable and/or erasable by electron emission from the emission tips. Methods of making and using this field-emission erasable programmable read-only memory (FEEPROM) cell are also provided.
摘要翻译：公开了一种场发射可擦除可编程只读存储器单元，其包括在该单元的一个或多个层上的一个或多个场致发射尖端。电池通过来自发射端的电子发射是可编程的和/或可擦除的。还提供了制造和使用该场发射可擦除可编程只读存储器（FEEPROM）单元的方法。

6. 发明授权

US08765541B1 Integrated circuit and a method to optimize strain inducing composites 有权
标题翻译：集成电路和优化应变诱导复合材料的方法
公开(公告)号：US08765541B1
公开(公告)日：2014-07-01
申请号：US13214056
申请日：2011-08-19
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/165 , H01L29/267
摘要： A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.
摘要翻译：公开了一种设计IC的方法，以提供应变诱导复合材料的均匀沉积。设计IC的方法包括：确定IC设计上的总应变诱导沉积区域。然后，将总应变诱导沉积区域与预定尺寸进行比较。当总应变诱导沉积面积低于预定尺寸时，修改虚拟扩散区域以增加总应变诱导沉积面积。最后，应变诱导沉积区域被优化。还公开了制造IC和IC的方法。

7. 发明授权

US08664725B1 Strain enhanced transistors with adjustable layouts 有权
标题翻译：具有可调布局的应变增强型晶体管
公开(公告)号：US08664725B1
公开(公告)日：2014-03-04
申请号：US13040538
申请日：2011-03-04
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/1054 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L27/3223 , H01L29/0692 , H01L29/41758 , H01L29/4238 , H01L29/66545 , H01L29/6681 , H01L29/76 , H01L29/7848 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.
摘要翻译：晶体管可以包括诸如矩形掺杂硅阱的半导体区域。栅极指可能与硅阱重叠。栅极指状物可以由多晶硅形成，并且可以沿着阱的长度彼此间隔开固定的栅极 - 栅极间隔。阱的边缘可以被场氧化物包围。可以在井中形成外延区域，以在位于栅极指的下方的沟道区域中产生压缩或拉伸应力。外延区可以形成源极 - 漏极端子。场氧化物的边缘可以与最近的栅极指边缘分开距离，该距离由计算机辅助设计工具自动调整并且可能大于栅极到栅极间距。可以提供虚拟门指结构以确保产生所需的应力水平。

8. 发明授权

US06624467B1 EEPROM active area castling 失效
标题翻译： EEPROM活动区域
公开(公告)号：US06624467B1
公开(公告)日：2003-09-23
申请号：US10193085
申请日：2002-07-09
申请人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
发明人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , H01L27/0203
摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.
摘要翻译：提供了一个“castled”活动区域面罩。壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。例如，在一个优选实施例中，城堡延伸部可以具有“T”形。由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

9. 发明授权

US06472272B1 Castled active area mask 失效
标题翻译：壁挂活动区域面罩
公开(公告)号：US06472272B1
公开(公告)日：2002-10-29
申请号：US09733850
申请日：2000-12-08
申请人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
发明人： Peter J. McElheny , Raminda U. Madurawe , Richard G. Smolen , Minchang Liang
IPC分类号： H01L21336
CPC分类号： H01L27/11519 , H01L27/0203 , Y10S438/942
摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.
摘要翻译：提供了一个“castled”活动区域面罩。壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

10. 发明授权

US08755218B2 Multiport memory element circuitry 有权
标题翻译：多端口存储元件电路
公开(公告)号：US08755218B2
公开(公告)日：2014-06-17
申请号：US13149249
申请日：2011-05-31
申请人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
发明人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
IPC分类号： G11C11/00
CPC分类号： G11C7/00 , G06F12/1425 , G11C8/16 , G11C2029/0411
摘要： Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.
摘要翻译：可以提供具有多端口存储器元件的集成电路。多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式