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1. 发明授权

US10504021B2 Neuromorphic event-driven neural computing architecture in a scalable neural network 有权
公开(公告)号：US10504021B2
公开(公告)日：2019-12-10
申请号：US14989579
申请日：2016-01-06
申请人： International Business Machines Corporation , Cornell University
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/00 , G06N3/06 , G06N3/04 , G06N3/063
CPC分类号： G06N3/06 , G06N3/04 , G06N3/049 , G06N3/063
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

2. 发明授权

US11580366B2 Neuromorphic event-driven neural computing architecture in a scalable neural network 有权
公开(公告)号：US11580366B2
公开(公告)日：2023-02-14
申请号：US16666142
申请日：2019-10-28
申请人： International Business Machines Corporation , Cornell University
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/06 , G06N3/04 , G06N3/063 , G06N3/049
摘要： An event-driven neural network including a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array that has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

3. 发明申请

US20200065658A1 NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALABLE NEURAL NETWORK 审中-公开
公开(公告)号：US20200065658A1
公开(公告)日：2020-02-27
申请号：US16666142
申请日：2019-10-28
申请人： International Business Machines Corporation , Cornell University
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
IPC分类号： G06N3/06 , G06N3/04 , G06N3/063
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

4. 发明授权

US10126428B2 Low power asynchronous GPS baseband processor 有权
公开(公告)号：US10126428B2
公开(公告)日：2018-11-13
申请号：US14380700
申请日：2013-02-25
申请人： Cornell University
发明人： Rajit Manohar , Benjamin Tang , Stephen Longfield , Sunil A. Bhave
IPC分类号： G01S19/24 , G01S19/29 , G01S19/30 , G01S5/10 , G01S19/34 , G01S19/37
摘要： Asynchronous Global Positioning System (GPS) baseband processor architectures with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly.

5. 发明申请

US20190007190A1 METHODS AND SYSTEMS FOR SYNCHRONIZATION BETWEEN MULTIPLE CLOCK DOMAINS 审中-公开
公开(公告)号：US20190007190A1
公开(公告)日：2019-01-03
申请号：US15992008
申请日：2018-05-29
申请人： Cornell University
发明人： Rajit Manohar , Sandra J. Jackson
IPC分类号： H04L7/00 , H04L12/863 , G06F1/12
CPC分类号： H04L7/0037 , G06F1/12 , H04L47/6245
摘要： A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

6. 发明申请

US20170214514A1 METHODS AND SYSTEMS FOR SYNCHRONIZATION BETWEEN MULTIPLE CLOCK DOMAINS 有权
公开(公告)号：US20170214514A1
公开(公告)日：2017-07-27
申请号：US15481407
申请日：2017-04-06
申请人： Cornell University
发明人： Rajit Manohar , Sandra J. Jackson
IPC分类号： H04L7/00 , H04L12/863
CPC分类号： H04L7/0037 , G06F1/12 , H04L47/6245
摘要： A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

7. 发明授权

US10705223B2 Low power asynchronous GPS baseband processor 有权
公开(公告)号：US10705223B2
公开(公告)日：2020-07-07
申请号：US16190001
申请日：2018-11-13
申请人： Cornell University
发明人： Rajit Manohar , Benjamin Tang , Stephen Longfield , Sunil A. Bhave
IPC分类号： G01S19/24 , G01S19/34 , G01S19/37
摘要： Asynchronous Global Positioning System (GPS) baseband processor architectures with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly.

8. 发明授权

US10355851B2 Methods and systems for synchronization between multiple clock domains 有权
公开(公告)号：US10355851B2
公开(公告)日：2019-07-16
申请号：US15992008
申请日：2018-05-29
申请人： Cornell University
发明人： Rajit Manohar , Sandra J. Jackson
IPC分类号： H04L7/00 , G06F1/12 , H04L12/863
摘要： A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

9. 发明授权

US09852253B2 Automated layout for integrated circuits with nonstandard cells 有权
公开(公告)号：US09852253B2
公开(公告)日：2017-12-26
申请号：US14891659
申请日：2014-05-19
申请人： Cornell University
发明人： Rajit Manohar , Robert Karmazin , Carlos Tadeo Ortega Otero
IPC分类号： G06F17/00 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F17/5081
摘要： Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.

10. 发明申请

US20160085898A1 AUTOMATED LAYOUT FOR INTEGRATED CIRCUITS WITH NONSTANDARD CELLS 有权
标题翻译：具有非标准电池的集成电路的自动布局
公开(公告)号：US20160085898A1
公开(公告)日：2016-03-24
申请号：US14891659
申请日：2014-05-19
申请人： CORNELL UNIVERSITY
发明人： Rajit Manohar , Robert Karmazin , Carlos Tadeo Ortega Otero
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F17/5081
摘要： Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit.
摘要翻译：公开了用于自动生成集成电路的物理布局的方法，系统和装置。基于电路描述将电路划分成一个或多个单元。该方法进一步检查在分区步骤期间生成的所有单元的单元布局的可用性。如果单元格的布局不可用，则该方法通过自动工具生成单元格的布局，并以与标准单元布局和布线工具兼容的标准单元的形式打包生成的布局。之后，生成的布局可能会导出到标准单元布局和布线工具。最后，标准单元放置和布线工具可以合并该电路的一个或多个单元的各个布局以产生该电路的布局。

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