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1. 发明申请

US20190087338A1 CACHE SYNONYM SYSTEM AND METHOD 审中-公开
公开(公告)号：US20190087338A1
公开(公告)日：2019-03-21
申请号：US15711165
申请日：2017-09-21
申请人： International Business Machines Corporation
发明人： Martin Recktenwald , Willm Hinrichs
IPC分类号： G06F12/0817 , G06F12/10
摘要： A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

2. 发明申请

US20190018773A1 SELECTIVE DOWNSTREAM CACHE PROCESSING FOR DATA ACCESS 审中-公开
公开(公告)号：US20190018773A1
公开(公告)日：2019-01-17
申请号：US15813751
申请日：2017-11-15
申请人： International Business Machines Corporation
发明人： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC分类号： G06F12/0817 , G06F12/0811 , G06F9/46
CPC分类号： G06F12/0828 , G06F9/467 , G06F12/0811 , G06F2212/60 , G06F2212/621
摘要： A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.

3. 发明授权

US09626293B2 Single-thread cache miss rate estimation 有权
公开(公告)号：US09626293B2
公开(公告)日：2017-04-18
申请号：US14918780
申请日：2015-10-21
申请人： International Business Machines Corporation
发明人： James J. Bonanno , Alper Buyuktosunoglu , Brian W. Curran , Willm Hinrichs , Christian Jacobi , Brian R. Prasky , Martin Recktenwald , Anthony Saporito , Vijayalakshmi Srinivasan , John-David Wellman
IPC分类号： G06F12/08 , G06F12/12 , G06F12/0831 , G06F12/0817 , G06F12/084 , G06F12/128
CPC分类号： G06F12/0831 , G06F9/3806 , G06F9/46 , G06F11/34 , G06F12/0824 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/123 , G06F12/128 , G06F2212/1024 , G06F2212/314 , G06F2212/601 , G06F2212/621 , G06F2212/622 , G06F2212/684
摘要： Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.

4. 发明授权

US09588893B2 Store cache for transactional memory 有权
公开(公告)号：US09588893B2
公开(公告)日：2017-03-07
申请号：US14537131
申请日：2014-11-10
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC分类号： G06F12/00 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/061 , G06F3/0638 , G06F3/0683 , G06F9/467 , G06F12/0811 , G06F12/084 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

5. 发明申请

US20160070654A1 EVICTING CACHED STORES 有权
标题翻译：高速缓存存储
公开(公告)号：US20160070654A1
公开(公告)日：2016-03-10
申请号：US14939052
申请日：2015-11-12
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
摘要： A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.
摘要翻译：一种基于商店压力来确定商店缓存条目的驱逐的工具。该工具由一个或多个计算机处理器确定一个或多个新的存储高速缓存条目分配的计数值。该工具确定是否超出新的存储缓存条目分配限制。超过了确定新的存储高速缓存条目分配限制的响应，工具确定一个或多个现有存储高速缓存条目的分配值，该分配值指示一个或多个现有存储高速缓存条目中的每一个的分配类别。该工具至少部分地基于一个或多个现有存储高速缓存条目的分配值，至少一个用于驱逐的分配类别。该工具程序确定用于逐出一个或多个现有存储高速缓存条目的逐出请求设置。

6. 发明申请

US20190087339A1 CACHE SYNONYM SYSTEM AND METHOD 审中-公开
公开(公告)号：US20190087339A1
公开(公告)日：2019-03-21
申请号：US15825639
申请日：2017-11-29
申请人： International Business Machines Corporation
发明人： Martin Recktenwald , Willm Hinrichs
IPC分类号： G06F12/0817 , G06F12/10
摘要： A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

7. 发明授权

US09658967B2 Evicting cached stores 有权
公开(公告)号：US09658967B2
公开(公告)日：2017-05-23
申请号：US14314461
申请日：2014-06-25
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC分类号： G06F12/00 , G06F12/121 , G06F12/0891
CPC分类号： G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
摘要： A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.

8. 发明授权

US09588894B2 Store cache for transactional memory 有权
标题翻译：存储事务内存缓存
公开(公告)号：US09588894B2
公开(公告)日：2017-03-07
申请号：US14578889
申请日：2014-12-22
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC分类号： G06F12/00 , G06F12/08 , G06F3/06 , G06F9/46
CPC分类号： G06F12/0808 , G06F3/061 , G06F3/0638 , G06F3/0683 , G06F9/467 , G06F12/0811 , G06F12/084 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.
摘要翻译：一种将一个或多个非事务存储和一个或多个线程专用事务存储合并到存储缓存中的存储缓冲器中的一个或多个高速缓存行模板中的方法。该方法接收线程特定非事务存储地址和第一数据，将存储地址映射到第一高速缓存线模板，并根据商店策略将第一数据合并到第一高速缓存行模板中。该方法还接收线程特定事务存储地址和第二数据，根据商店策略将线程专用存储地址映射到第二高速缓存线模板中。该方法进一步将高速缓存行模板的副本写回高速缓存，并使第三个高速缓存行模板无效，从而将第三个高速缓存行模板从存储地址映射中释放出来。

9. 发明申请

US20160132431A1 STORE CACHE FOR TRANSACTIONAL MEMORY 有权
公开(公告)号：US20160132431A1
公开(公告)日：2016-05-12
申请号：US14578889
申请日：2014-12-22
申请人： International Business Machines Corporation
发明人： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/061 , G06F3/0638 , G06F3/0683 , G06F9/467 , G06F12/0811 , G06F12/084 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

10. 发明授权

US10970214B2 Selective downstream cache processing for data access 有权
公开(公告)号：US10970214B2
公开(公告)日：2021-04-06
申请号：US16436104
申请日：2019-06-10
申请人： International Business Machines Corporation
发明人： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC分类号： G06F12/00 , G06F12/0817 , G06F9/46 , G06F12/0811
摘要： A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.

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