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1. 发明申请

US20160134363A1 Dynamic Optical Channel Sparing in an Industry Standard Input/Output Subsystem 有权
标题翻译：行业标准输入/输出子系统中的动态光通道备用
公开(公告)号：US20160134363A1
公开(公告)日：2016-05-12
申请号：US14730338
申请日：2015-06-04
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Daniel M. Dreps , Nanju Na , Suzanne M. Nolen
IPC分类号： H04B10/038 , H04Q11/00 , H04L12/40 , G02B6/35 , H04L12/707
CPC分类号： H04B10/038 , G06F13/00 , H04B10/075 , H04B10/25 , H04L12/40182 , H04L45/22 , H04Q11/0066 , H04Q2011/0081
摘要： Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.
摘要翻译：提供了一种在包括实现工业标准光总线的输入/输出子系统的数据处理系统中用于处理光总线中的光信道故障的机制。该机制通过输入/输出（I / O）子系统的故障检测逻辑检测光总线的光通道故障。该机制由I / O子系统的控制器向I / O子系统的信道路由逻辑发送控制信号，以控制数据处理系统的有效总线通道与光总线的光通道之间数据信号的路由响应于检测到光通道的故障。该机制通过信道路由逻辑来控制有源总线通道和光信道之间的数据信号的路由，从而进一步使用故障光信道，并使用备用光信道而不是故障光信道。

2. 发明申请

US20150286601A1 IMPLEMENTING SIDEBAND CONTROL STRUCTURE FOR PCIE CABLE CARDS AND IO EXPANSION ENCLOSURES 有权
标题翻译：实施PCIE电缆卡和IO扩展外壳的侧边控制结构
公开(公告)号：US20150286601A1
公开(公告)日：2015-10-08
申请号：US14243999
申请日：2014-04-03
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jeffery D. Haumont , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4221 , G06F13/4081
摘要： A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现用于连接到计算机系统中的输入/输出（IO）扩展机柜的外围组件互连Express（PCIE）附加卡或电缆卡的边带控制结构。系统固件可以唯一地识别存在于系统单元中的PCIE插槽中的电缆卡。机箱管理功能使用集成在至少电缆中的边带控制路径，提供边带控制信令，并在电缆卡和IO机箱之间提供PCIE信令通道。

3. 发明授权

US09548808B2 Dynamic optical channel sparing in an industry standard input/output subsystem 有权
标题翻译：动态光通道保留在工业标准输入/输出子系统中
公开(公告)号：US09548808B2
公开(公告)日：2017-01-17
申请号：US14538118
申请日：2014-11-11
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Daniel M. Dreps , Nanju Na , Suzanne M. Nolen
IPC分类号： H04B10/038 , H04Q11/00 , H04L12/40 , H04L12/707
CPC分类号： H04B10/038 , G06F13/00 , H04B10/075 , H04B10/25 , H04L12/40182 , H04L45/22 , H04Q11/0066 , H04Q2011/0081
摘要： Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.
摘要翻译：提供了一种在包括实现工业标准光总线的输入/输出子系统的数据处理系统中用于处理光总线中的光信道故障的机制。该机制通过输入/输出（I / O）子系统的故障检测逻辑检测光总线的光通道故障。该机制由I / O子系统的控制器向I / O子系统的信道路由逻辑发送控制信号，以控制数据处理系统的有效总线通道与光总线的光通道之间的数据信号的路由响应于检测到光通道的故障。该机制通过信道路由逻辑来控制有源总线通道和光信道之间的数据信号的路由，从而进一步使用故障光信道，并使用备用光信道而不是故障光信道。

4. 发明申请

US20150286602A1 IMPLEMENTING SIDEBAND CONTROL STRUCTURE FOR PCIE CABLE CARDS AND IO EXPANSION ENCLOSURES 有权
公开(公告)号：US20150286602A1
公开(公告)日：2015-10-08
申请号：US14628203
申请日：2015-02-20
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jeffery D. Haumont , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4221 , G06F13/4081
摘要： A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

5. 发明授权

US08799702B2 Cable redundancy and failover for multi-lane PCI express IO interconnections 有权
标题翻译：多通道PCI Express IO互连的电缆冗余和故障转移
公开(公告)号：US08799702B2
公开(公告)日：2014-08-05
申请号：US13680202
申请日：2012-11-19
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jay R. Herring , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F11/00
CPC分类号： G06F11/2005 , G06F11/2007 , G06F13/4022 , G06F2213/0026
摘要： Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.
摘要翻译：提供了用于为第一PCIE桥和第一输入/输出（IO）设备之间的连接提供故障切换操作的方法和装置。使用第一PCIE桥的第一组通道，通过第一链路在第一PCIE桥和第一IO设备之间交换第一组总线位。响应于检测到第一链路中的故障，在PCIE桥端，第一组通道与第一PCIE桥的第二组通道交换，用于在第一PCIE桥与第一PCIE桥之间交换第二组总线位使用第二组通道在第二链路上的第一IO设备，所述第二链路将第二PCIE桥连接到第二IO设备。响应于检测到第一链路中的故障，在IO设备端，第一组通道与第二组通道交换，用于在第一PCIE桥和第一IO设备之间交换第二组总线位，使用第二组通道的第二个链接。

6. 发明申请

US20180074992A1 IMPLEMENTING SIDEBAND CONTROL STRUCTURE FOR PCIE CABLE CARDS AND IO EXPANSION ENCLOSURES 有权
公开(公告)号：US20180074992A1
公开(公告)日：2018-03-15
申请号：US15822124
申请日：2017-11-25
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jeffery D. Haumont , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4221 , G06F13/4081
摘要： A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

7. 发明授权

US09870335B2 Implementing sideband control structure for PCIE cable cards and IO expansion enclosures 有权
公开(公告)号：US09870335B2
公开(公告)日：2018-01-16
申请号：US14243999
申请日：2014-04-03
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jeffery D. Haumont , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F13/20 , G06F13/42 , G06F13/40
CPC分类号： G06F13/4221 , G06F13/4081
摘要： A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

8. 发明授权

US09870336B2 Implementing sideband control structure for PCIE cable cards and IO expansion enclosures 有权
公开(公告)号：US09870336B2
公开(公告)日：2018-01-16
申请号：US14628203
申请日：2015-02-20
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jeffery D. Haumont , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F13/20 , G06F13/42 , G06F13/40
CPC分类号： G06F13/4221 , G06F13/4081
摘要： A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.

9. 发明申请

US20160134362A1 Dynamic Optical Channel Sparing in an Industry Standard Input/Output Subsystem 有权
公开(公告)号：US20160134362A1
公开(公告)日：2016-05-12
申请号：US14538118
申请日：2014-11-11
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Daniel M. Dreps , Nanju Na , Suzanne M. Nolen
IPC分类号： H04B10/038 , H04Q11/00 , H04L12/40 , G02B6/35 , H04L12/707
CPC分类号： H04B10/038 , G06F13/00 , H04B10/075 , H04B10/25 , H04L12/40182 , H04L45/22 , H04Q11/0066 , H04Q2011/0081
摘要： Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.

10. 发明授权

US08645747B2 Cable redundancy and failover for multi-lane PCI express IO interconnections 失效
公开(公告)号：US08645747B2
公开(公告)日：2014-02-04
申请号：US13680430
申请日：2012-11-19
申请人： International Business Machines Corporation
发明人： Patrick A. Buckland , Jay R. Herring , Gregory M. Nordstrom , William A. Thompson
IPC分类号： G06F11/00
CPC分类号： G06F13/4068 , G06F11/2007 , G06F11/2017 , G06F2201/85
摘要： Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.

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