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1. 发明授权

US09735894B2 High performance receiver architecture and methods thereof 有权
公开(公告)号：US09735894B2
公开(公告)日：2017-08-15
申请号：US14665818
申请日：2015-03-23
申请人： Intel IP Corporation
发明人： Mohammed Alam , Patrick Rakers
IPC分类号： H04B1/26 , H04B15/02 , H03D7/14
CPC分类号： H04B15/02 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： A user equipment (UE), receiver and method are generally described herein. The UE may include a mixer, a local oscillator (LO) and an analog-to-digital converter (ADC). The mixer may downconvert a differential radio frequency (RF) signal using LO signals and provide downconverted signals to the ADC. The mixer may provide decoupled lowpass filtering. The lowpass filter capacitors may retain charge when discharging is completed. For each differential signal, the mixer may have an input pullup resistor, first switches receiving the signal and driven by different LO signals, second switches receiving signals from the first switches such that connected pairs of switches may have driven by different LO signals, an ADC input resistor, charging capacitors each connected between first switches driven by the same LO signal, and grounding capacitors each connected to second switches associated with different RF signal outputs and driven by different LO signals.

2. 发明申请

US20160285567A1 HIGH PERFORMANCE RECEIVER ARCHITECTURE AND METHODS THEREOF 有权
标题翻译：高性能接收机架构及其方法
公开(公告)号：US20160285567A1
公开(公告)日：2016-09-29
申请号：US14665818
申请日：2015-03-23
申请人： Intel IP Corporation
发明人： Mohammed Alam , Patrick Rakers
IPC分类号： H04B15/02 , H03D7/14
CPC分类号： H04B15/02 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： A user equipment (UE), receiver and method are generally described herein. The UE may include a mixer, a local oscillator (LO) and an analog-to-digital converter (ADC). The mixer may downconvert a differential radio frequency (RF) signal using LO signals and provide downconverted signals to the ADC. The mixer may provide decoupled lowpass filtering. The lowpass filter capacitors may retain charge when discharging is completed. For each differential signal, the mixer may have an input pullup resistor, first switches receiving the signal and driven by different LO signals, second switches receiving signals from the first switches such that connected pairs of switches may have driven by different LO signals, an ADC input resistor, charging capacitors each connected between first switches driven by the same LO signal, and grounding capacitors each connected to second switches associated with different RF signal outputs and driven by different LO signals.
摘要翻译：本文一般地描述用户设备（UE），接收机和方法。 UE可以包括混频器，本地振荡器（LO）和模数转换器（ADC）。混频器可以使用LO信号对差分射频（RF）信号进行下变频，并向ADC提供下变频信号。混频器可以提供解耦的低通滤波。当放电完成时，低通滤波电容可能会保持充电。对于每个差分信号，混频器可以具有输入上拉电阻，首先接收信号并由不同的LO信号驱动，第二开关从第一开关接收信号，使得连接的开关对可以由不同的LO信号驱动，ADC 输入电阻器，每个连接在由相同LO信号驱动的第一开关之间的充电电容器以及各自连接到与不同RF信号输出相关联的第二开关并由不同LO信号驱动的接地电容器。

3. 发明授权

US09008231B2 Signal duty cycle reduction 有权
标题翻译：信号占空比减少
公开(公告)号：US09008231B2
公开(公告)日：2015-04-14
申请号：US13907796
申请日：2013-05-31
申请人： Intel IP Corporation
发明人： Tomoyuki Arai , Patrick Rakers
IPC分类号： H03D3/00 , H04L27/14
CPC分类号： H04L27/3405 , H03K5/1565
摘要： A method may include receiving a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I− signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q− signal”). The method may further include outputting a truncated I+ signal, a truncated I− signal, a truncated Q+ signal, and a truncated Q− signal. The method may further include generating the truncated I+ signal based on the I+ and Q+ signals and a complement of the truncated Q− signal, generating the truncated I− signal based on the I− and Q− signals and a complement of the truncated Q+ signal, generating the truncated Q+ signal based on the I− and Q+ signals and a complement of the truncated I+ signal, and generating the truncated Q− signal based on the I+ and Q− signals and a complement of the truncated I− signal.
摘要翻译：一种方法可以包括：接收正同相（“I”）信道信号（“I +信号”），负I信道信号（“I-信号”），正正交相位（“Q”） - 通道信号（“Q +信号”）和负Q通道信号（“Q-信号”）。该方法还可以包括输出截断的I +信号，截断的I信号，截短的Q +信号和截短的Q信号。该方法还可以包括基于I +和Q +信号产生截断的I +信号，以及截断的Q信号的补码，基于I和Q信号产生截断的I信号以及截短的Q +信号的补码基于I和Q +信号和截断的I +信号的补码产生截断的Q +信号，并且基于I +和Q-信号以及截断的I信号的互补产生截断的Q信号。

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