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1. 发明公开

US20230197677A1 PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY 审中-公开
公开(公告)号：US20230197677A1
公开(公告)日：2023-06-22
申请号：US17557622
申请日：2021-12-21
申请人： Intel Corporation
发明人： Adel A. Elsherbini , Stephen R. Van Doren , Ritu Gupta , Gerald S. Pasdast , Robert J. Munoz , Shawna M. Liff
IPC分类号： H01L25/065
CPC分类号： H01L25/0652 , H01L2225/06548
摘要： A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

2. 发明授权

US11251171B2 Removable interposer 有权
公开(公告)号：US11251171B2
公开(公告)日：2022-02-15
申请号：US16007867
申请日：2018-06-13
申请人： Intel Corporation
发明人： Michael Rifani , Robert J. Munoz , Thomas P. Thomas , John Mark Matson , Kursad Kiziloglu
IPC分类号： H01L25/18 , H01L23/32 , G02B6/12 , H01L23/538
摘要： Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

3. 发明授权

US09485200B2 Network switch with external buffering via looparound path 有权
标题翻译：网络交换机通过环绕路径进行外部缓冲
公开(公告)号：US09485200B2
公开(公告)日：2016-11-01
申请号：US13746080
申请日：2013-01-21
申请人： Intel Corporation
发明人： Robert J. Munoz
IPC分类号： G06F9/455 , G06F9/46 , H04L12/28 , H04L12/861 , H04L12/933 , H04L12/931 , H04L12/835 , H04L12/833 , H04L12/801
CPC分类号： H04L49/9078 , G06F15/167 , H04L47/12 , H04L47/30 , H04L47/31 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments process data packets received by a network switch coupled to an external buffering device. The network switch determines a queue of an internal buffer of the network switch associated with a flow of the received packet and determines whether the received packet should be forwarded to the external buffering device. If the received packet should be forwarded to the external buffering device, the network switch sets an external buffering active indicator indicating that the network switch is in an external buffering mode for the flow, tags the received packet with metadata, and forwards the packet to the external buffering device. The external buffering device stores the forwarded packet in a queue of a memory of the external buffering device corresponding to the tagged metadata of the forwarded packet. The network switch processes packets stored in the internal buffer of the network switch.
摘要翻译：描述的实施例处理由耦合到外部缓冲设备的网络交换机接收的数据分组。网络交换机确定与接收到的分组的流相关联的网络交换机的内部缓冲器的队列，并确定接收到的分组是否应转发到外部缓冲设备。如果接收到的数据包应该转发到外部缓冲设备，则网络交换机设置外部缓冲活动指示符，指示网络交换机处于流量的外部缓冲模式，用元数据对接收到的数据包进行标记，并将数据包转发到外部缓冲设备外部缓冲装置将转发的分组存储在与所转发的分组的标记的元数据相对应的外部缓冲装置的存储器的队列中。网络交换机处理存储在网络交换机的内部缓冲区中的数据包。

4. 发明申请

US20190385994A1 REMOVABLE INTERPOSER 审中-公开
公开(公告)号：US20190385994A1
公开(公告)日：2019-12-19
申请号：US16007867
申请日：2018-06-13
申请人： Intel Corporation
发明人： Michael Rifani , Robert J. Munoz , Thomas P. Thomas , John Mark Matson , Kursad Kiziloglu
IPC分类号： H01L25/18 , H01L23/32 , H01L23/538 , G02B6/12
摘要： Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

5. 发明授权

US09755947B2 Hierarchical self-organizing classification processing in a network switch 有权
公开(公告)号：US09755947B2
公开(公告)日：2017-09-05
申请号：US13746104
申请日：2013-01-21
申请人： Intel Corporation
发明人： Robert J. Munoz
IPC分类号： H04L12/751 , G06F9/30 , G06F9/38 , G06F9/26 , H04L12/933 , H04L12/935 , H04L12/851 , H04L12/931
CPC分类号： H04L45/08 , G06F9/264 , G06F9/30058 , G06F9/30061 , G06F9/30094 , G06F9/3885 , H04L47/2441 , H04L47/2483 , H04L49/101 , H04L49/109 , H04L49/3009 , H04L49/351
摘要： Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are stored in the internal database, the switch tags the received packet with metadata and forwards the packet to the network processor. The network processor determines one or more rules for classifying and processing the forwarded packet in a classification database of the network processor and updates statistics corresponding to each rule. The network processor classifies and processes the packet in accordance with the rules and updates the internal database of the switch.

6. 发明公开

US20230187407A1 FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE 审中-公开
公开(公告)号：US20230187407A1
公开(公告)日：2023-06-15
申请号：US17548304
申请日：2021-12-10
申请人： Intel Corporation
发明人： Carleton L. Molnar , Adel A. Elsherbini , Tanay Karnik , Shawna M. Liff , Robert J. Munoz , Julien Sebot , Johanna M. Swan , Nevine Nassif , Gerald S. Pasdast , Krishna Bharath , Neelam Chandwani , Dmitri E. Nikonov
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00
CPC分类号： H01L25/0652 , H01L23/481 , H01L24/08 , H01L24/20 , H01L2224/2101 , H01L2224/08147 , H01L2924/37001 , H01L2924/1427
摘要： A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

7. 发明公开

US20230187362A1 PACKAGING ARCHITECTURE WITH PATTERNED THROUGH-DIELECTRIC VIAS AND REDISTRIBUTION LAYERS 审中-公开
公开(公告)号：US20230187362A1
公开(公告)日：2023-06-15
申请号：US17548078
申请日：2021-12-10
申请人： Intel Corporation
发明人： Adel A. Elsherbini , Christopher M. Pelto , Kimin Jun , Brandon M. Rawlings , Shawna M. Liff , Bradley A. Jackson , Robert J. Munoz , Johanna M. Swan
IPC分类号： H01L23/538 , H01L25/065 , H01L23/498 , H01L25/00 , H01L23/00
CPC分类号： H01L23/5383 , H01L25/0652 , H01L23/49894 , H01L25/50 , H01L24/96
摘要： A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

8. 发明公开

US20230170327A1 INTEGRATED PACKAGING ARCHITECTURE WITH SOLDER AND NON-SOLDER INTERCONNECTS 审中-公开
公开(公告)号：US20230170327A1
公开(公告)日：2023-06-01
申请号：US17538603
申请日：2021-11-30
申请人： Intel Corporation
发明人： Jin Yang , David Shia , Adel A. Elsherbini , Christopher M. Pelto , Kimin Jun , Bradley A. Jackson , Robert J. Munoz , Shawna M. Liff , Johanna M. Swan
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L25/50 , H01L25/0652 , H01L2225/06517 , H01L24/08
摘要： A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

9. 发明授权

US10791057B2 Techniques for packet transmit scheduling 有权
公开(公告)号：US10791057B2
公开(公告)日：2020-09-29
申请号：US16175734
申请日：2018-10-30
申请人： Intel Corporation
发明人： Sarig Livne , Ben-Zion Friedman , Ronen Aharon Hyatt , Nir Tiser , Robert J. Munoz
IPC分类号： H04L12/815 , H04L12/741 , H04L12/911 , H04L12/927 , H04L12/825
摘要： Techniques to schedule transmission of a packet from a computing platform include calculating adjustments to portions of the packet to cause corrections to at least one portion of the packet. An adjustment to a scheduled transmission of the packet is made based on the corrections.

10. 发明授权

US09444737B2 Packet data processor in a communications processor architecture 有权
标题翻译：分组数据处理器在通信处理器架构中
公开(公告)号：US09444737B2
公开(公告)日：2016-09-13
申请号：US13756849
申请日：2013-02-01
申请人： Intel Corporation
发明人： Robert J. Munoz
IPC分类号： H04L12/747 , H04L12/741
CPC分类号： H04L45/742 , H04L45/74 , H04L45/7457 , H04L47/2483 , H04L67/28
摘要： Described embodiments provide a network processor having a hardware accelerator that identifies a received packet and, based on a flow identification associated with the received packet, might pre-fetch pre-established portions of data from the received packet into local data memory (e.g., local data cache) for processing by a general purpose processor core. In addition to the packet data, the software necessary for the general-purpose processor core to process the data might also be pre-fetched into local instruction memory (e.g., local instruction cache). The flow identification might be used to select different portions of the packet and different software to be pre-fetched.
摘要翻译：所描述的实施例提供一种具有硬件加速器的网络处理器，该硬件加速器识别所接收的分组，并且基于与所接收的分组相关联的流标识可将预先建立的数据部分从所接收的分组预取到本地数据存储器（例如，本地数据缓存），用于由通用处理器核心处理。除了分组数据之外，通用处理器核心处理数据所需的软件也可以被预取到本地指令存储器（例如，本地指令高速缓存）中。流标识可以用于选择分组的不同部分和要预取的不同软件。

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