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1. 发明授权

US09619672B2 Method and apparatus for secure execution using a secure memory partition 有权
公开(公告)号：US09619672B2
公开(公告)日：2017-04-11
申请号：US14583062
申请日：2014-12-24
申请人： Intel Corporation
发明人： Millind Mittal
IPC分类号： G06F12/14 , G06F21/72 , G06F21/60 , G06F21/78
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

2. 发明授权

US09547779B2 Method and apparatus for secure execution using a secure memory partition 有权
标题翻译：使用安全存储器分区进行安全执行的方法和装置
公开(公告)号：US09547779B2
公开(公告)日：2017-01-17
申请号：US14583056
申请日：2014-12-24
申请人： Intel Corporation
发明人： Millind Mittal
IPC分类号： G06F21/78 , G06F12/14 , G06F21/72 , G06F21/60
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor includes a plurality of general purpose registers and cryptographic logic to encrypt and decrypt information. The cryptographic logic is to support a Data Encryption Standard (DES) algorithm, a triple DES (3DES) algorithm, a Rivest-Shamir-Adleman (RSA) algorithm, and a Diffie Hellman algorithm. The processor also includes a plurality of memory partition registers to define a physical address range in a dynamic random access memory for use as a secure memory partition. The processor also includes a plurality of execution units coupled to the plurality of general purpose registers, the plurality of memory partition registers, and the cryptographic logic. The processor also includes secure partition enforcement logic coupled to the plurality of execution units and the memory partition registers, the secure partition enforcement logic to selectively permit read or write access to the dynamic random access memory.
摘要翻译：处理器包括多个通用寄存器和加密和解密信息的加密逻辑。密码逻辑是支持数据加密标准（DES）算法，三重DES（3DES）算法，Rivest-Shamir-Adleman（RSA）算法和Diffie Hellman算法。处理器还包括多个存储器分区寄存器，以在动态随机存取存储器中定义用作安全存储器分区的物理地址范围。处理器还包括耦合到多个通用寄存器，多个存储器分区寄存器和加密逻辑的多个执行单元。所述处理器还包括耦合到所述多个执行单元和所述存储器分区寄存器的安全分区强制逻辑，所述安全分区执行逻辑选择性地允许对所述动态随机存取存储器的读或写访问。

3. 发明授权

US09507962B2 Method and apparatus for secure execution using a secure memory partition 有权
公开(公告)号：US09507962B2
公开(公告)日：2016-11-29
申请号：US14583054
申请日：2014-12-24
申请人： Intel Corporation
发明人： Millind Mittal
IPC分类号： G06F21/44 , G06F21/72 , G06F12/14 , G06F21/60 , G06F9/24
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

4. 发明授权

US09323954B2 Method and apparatus for secure execution using a secure memory partition 有权
公开(公告)号：US09323954B2
公开(公告)日：2016-04-26
申请号：US14583051
申请日：2014-12-24
申请人： Intel Corporation
发明人： Millind Mittal
IPC分类号： G06F21/72 , G06F12/14 , G06F21/60 , G06F21/57
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

5. 发明授权

US09141387B2 Processor executing unpack and pack instructions specifying two source packed data operands and saturation 有权
标题翻译：处理器执行解包和包指令，指定两个源压缩数据操作数和饱和度
公开(公告)号：US09141387B2
公开(公告)日：2015-09-22
申请号：US13730832
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30 , G06F7/499
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一打包数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

6. 发明授权

US08793475B2 Method and apparatus for unpacking and moving packed data 有权
标题翻译：打包和移动打包数据的方法和装置
公开(公告)号：US08793475B2
公开(公告)日：2014-07-29
申请号：US13730837
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一打包数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

7. 发明授权

US09389858B2 Orderly storing of corresponding packed bytes from first and second source registers in result register 有权
标题翻译：在结果寄存器中有序地存储来自第一和第二源寄存器的相应打包字节
公开(公告)号：US09389858B2
公开(公告)日：2016-07-12
申请号：US13730846
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315 , G06F9/30 , G06F7/499
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一打包数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

8. 发明授权

US09305183B2 Method and apparatus for secure execution using a secure memory partition 有权
公开(公告)号：US09305183B2
公开(公告)日：2016-04-05
申请号：US14583060
申请日：2014-12-24
申请人： Intel Corporation
发明人： Millind Mittal
IPC分类号： G06F21/79 , G06F21/72 , G06F12/14 , G06F21/60
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

9. 发明授权

US09223572B2 Interleaving half of packed data elements of size specified in instruction and stored in two source registers 有权
标题翻译：交换指令中指定的大小的包装数据元素的一半，并存储在两个源寄存器中
公开(公告)号：US09223572B2
公开(公告)日：2015-12-29
申请号：US13730835
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315 , G06F9/30 , G06F7/499
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一打包数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

10. 发明授权

US09116687B2 Packing in destination register half of each element with saturation from two source packed data registers 有权
标题翻译：目的寄存器的包装从两个源打包数据寄存器中饱和的每个元件的一半
公开(公告)号：US09116687B2
公开(公告)日：2015-08-25
申请号：US13730842
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315 , G06F9/30 , G06F7/499
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
摘要翻译：一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。从第一源寄存器接收第一压缩数据元素和第三打包数据元素。从第二源寄存器接收第二打包数据元素和第四打包数据元素。所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素数据元素。

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