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1. 发明申请

US20230102991A1 SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR 有权
公开(公告)号：US20230102991A1
公开(公告)日：2023-03-30
申请号：US17484542
申请日：2021-09-24
申请人： Intel Corporation
发明人： Michael Mishaeli , Edward Brazil , Bryan J. Gran , Ohad Itzhaki
IPC分类号： G06F11/22 , G06F11/273 , G06F11/263
摘要： Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

2. 发明授权

US11029953B2 Branch prediction unit in service of short microcode flows 有权
公开(公告)号：US11029953B2
公开(公告)日：2021-06-08
申请号：US16453704
申请日：2019-06-26
申请人： Intel Corporation
发明人： Michael Mishaeli , Ido Ouziel , Jared Warner Stark, IV
IPC分类号： G06F9/30 , G06F9/38 , G06F12/12
摘要： Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.

3. 发明授权

US10261790B2 Memory copy instructions, processors, methods, and systems 有权
公开(公告)号：US10261790B2
公开(公告)日：2019-04-16
申请号：US15086686
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： Michael Mishaeli
IPC分类号： G06F9/30 , G06F9/38
摘要： A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory operand, and an initial amount of data to be copied from the source memory operand to the destination memory operand. An execution unit, in response to the memory copy instruction, is to copy a first portion of data from the source memory operand to the destination memory operand before an interruption. A descending copy direction is to be used when the source and destination memory operands overlap. In response to the interruption, when the descending copy direction is used, the execution unit is to store a remaining amount of data to be copied, but is not to indicate a different start of the source memory operand, and is not to indicate a different start of the destination memory operand.

4. 发明授权

US09898330B2 Compacted context state management 有权
公开(公告)号：US09898330B2
公开(公告)日：2018-02-20
申请号：US14076341
申请日：2013-11-11
申请人： Intel Corporation
发明人： Atul Khare , Leena Puthiyedath , Asit Mallick , Jim Coke , Michael Mishaeli , Gilbert Neiger , Vivekananthan Sanjeepan , Jason Brandt
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/461 , G06F9/30003 , G06F9/30043 , G06F9/30101
摘要： Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

5. 发明授权

US09891695B2 Flushing and restoring core memory content to external memory 有权
公开(公告)号：US09891695B2
公开(公告)日：2018-02-13
申请号：US14751889
申请日：2015-06-26
申请人： Intel Corporation
发明人： Alexander Gendler , Ariel Berkovits , Michael Mishaeli , Nadav Shulman , Sameer Desai , Shani Rehana , Ittai Anati , Hisham Shafi
IPC分类号： G06F1/32 , G06F12/08 , G06F12/14 , G06F12/0868 , G06F12/0804 , G06F12/0888
CPC分类号： G06F1/3287 , G06F12/0804 , G06F12/0868 , G06F12/0888 , G06F12/1433 , G06F2212/1052 , G06F2212/311 , G06F2212/621
摘要： A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

6. 发明授权

US09501132B2 Instruction and logic for store broadcast and power management 有权
标题翻译：商店广播和电源管理的指导和逻辑
公开(公告)号：US09501132B2
公开(公告)日：2016-11-22
申请号：US14453341
申请日：2014-08-06
申请人： Intel Corporation
发明人： Michael Mishaeli , Stanislav Shwartsman , Gal Ofir , Yulia Kurolap
IPC分类号： G06F1/32 , G06F9/30 , G06F15/78
CPC分类号： G06F1/3287 , G06F1/32 , G06F9/30145 , G06F15/7807 , Y02D10/171 , Y02D50/20
摘要： A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.
摘要翻译：处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率本地门控电路。执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。

7. 发明授权

US08935514B2 Optimizing performance of instructions based on sequence detection or information associated with the instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令的性能
公开(公告)号：US08935514B2
公开(公告)日：2015-01-13
申请号：US14012344
申请日：2013-08-28
申请人： Intel Corporation
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/40 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

8. 发明授权

US11023233B2 Methods, apparatus, and instructions for user level thread suspension 有权
公开(公告)号：US11023233B2
公开(公告)日：2021-06-01
申请号：US15019112
申请日：2016-02-09
申请人： INTEL CORPORATION
发明人： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
IPC分类号： G06F9/30 , G06F13/40 , G06F9/48 , G06F9/38
摘要： A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

9. 发明授权

US10775434B2 System, apparatus and method for probeless field scan of a processor 有权
公开(公告)号：US10775434B2
公开(公告)日：2020-09-15
申请号：US16142591
申请日：2018-09-26
申请人： Intel Corporation
发明人： Michael Mishaeli , Larisa Novakovsky , Edward Brazil , Alexander Gendler
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G06F1/3203 , G06F11/27
摘要： In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

10. 发明授权

US10656697B2 Processor core power event tracing 有权
公开(公告)号：US10656697B2
公开(公告)日：2020-05-19
申请号：US15911577
申请日：2018-03-05
申请人： Intel Corporation
发明人： Tsvika Kurts , Beeman C. Strong , Richard B. O'Connor , Michael W. Chynoweth , Rajshree A. Chabukswar , Avner Lottem , Itamar Kazachinsky , Michael Mishaeli , Anthony Wojciechowski , Vikas R. Vasisht
IPC分类号： G06F1/32 , G06F11/34 , G06F11/30 , G06F1/3206
摘要： A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

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