专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190196838A1 APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR 审中-公开
公开(公告)号：US20190196838A1
公开(公告)日：2019-06-27
申请号：US16289075
申请日：2019-02-28
申请人： Intel Corporation
发明人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
IPC分类号： G06F9/38 , G06F15/80 , G06F9/46 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3836 , G06F9/3855 , G06F9/3861 , G06F9/3877 , G06F9/46 , G06F15/7867 , G06F15/7892 , G06F15/80
摘要： An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

2. 发明授权

US09542193B2 Memory address collision detection of ordered parallel threads with bloom filters 有权
标题翻译：带有绽放滤波器的有序并行线程的内存地址冲突检测
公开(公告)号：US09542193B2
公开(公告)日：2017-01-10
申请号：US13730704
申请日：2012-12-28
申请人： Intel Corporation
发明人： Enrique De Lucas , Pedro Marcuello , Oren Ben-Kiki , Ilan Pardo , Yuval Yosef
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/3834 , G06F9/3851 , G06F9/3857 , G06F9/3867
摘要： A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.
摘要翻译：描述了一种具有负载碰撞检测电路的半导体芯片，该电路包括第一起爆滤波器电路。半导体芯片具有存储冲突检测电路，该电路包括第二盛盛滤波器电路。该半导体芯片具有能够执行与负载碰撞检测电路和存储冲突检测电路耦合的有序并行线程的一个或多个处理单元。负载碰撞检测电路和存储碰撞检测电路是检测较年轻的存储器用于所述线程和较小负载的负载操作，用于所述线程的存储操作。

3. 发明授权

US09417873B2 Apparatus and method for a hybrid latency-throughput processor 有权
标题翻译：用于混合延迟吞吐量处理器的装置和方法
公开(公告)号：US09417873B2
公开(公告)日：2016-08-16
申请号：US13730055
申请日：2012-12-28
申请人： INTEL CORPORATION
发明人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
IPC分类号： G06F15/78 , G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3836 , G06F9/3855 , G06F9/3861 , G06F9/3877 , G06F9/46 , G06F15/7867 , G06F15/7892 , G06F15/80
摘要： An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
摘要翻译：描述了用于在处理设备上执行延迟优化的执行逻辑和吞吐量优化的执行逻辑的装置和方法。例如，根据一个实施例的处理器包括：执行第一类型的程序代码的等待时间优化的执行逻辑; 吞吐量优化执行逻辑以执行第二类型的程序代码，其中所述第一类型的程序代码和所述第二类型的程序代码被设计用于相同的指令集架构; 识别过程中的第一类型的程序代码和第二类型的程序代码的逻辑，并且将用于执行的第一类型的程序代码分配在延迟优化的执行逻辑和第二类型的程序代码上以便在吞吐量 - 优化的执行逻辑。

4. 发明申请

US20160109925A1 AN APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM 审中-公开
标题翻译：降低平台中空闲链路功率的设备
公开(公告)号：US20160109925A1
公开(公告)日：2016-04-21
申请号：US14978340
申请日：2015-12-22
申请人： Intel Corporation
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.
摘要翻译：提供了一种芯片系统（SoC），包括处理核心和根系统。事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测电路被禁用，并且不保持共模电压。根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

5. 发明授权

US10095517B2 Apparatus and method for retrieving elements from a linked structure 有权
公开(公告)号：US10095517B2
公开(公告)日：2018-10-09
申请号：US14979236
申请日：2015-12-22
申请人： Intel Corporation
发明人： Oren Ben-Kiki , Ilan Pardo
IPC分类号： G06F9/30 , G06F9/34 , G06F9/345
摘要： An apparatus and method are described for retrieving elements from a linked structure. For example, one embodiment of an apparatus comprises: a decode unit to decode a first instruction, the first instruction to utilize a current address value, an end address value, and an offset; and an execution unit to execute the first instruction to cause the execution unit to compare the current address value with the end address value, the execution unit to perform no additional operation with respect to the first instruction if the current address value is equal to the end address value; and if the current address value is not equal to the end address value, then the execution unit to add the offset value to the current address value to identify a next address pointer within an element structure, the execution unit to further set the current address value equal to the next address pointer.

6. 发明授权

US10089113B2 Apparatus and method for low-latency invocation of accelerators 有权
公开(公告)号：US10089113B2
公开(公告)日：2018-10-02
申请号：US15282082
申请日：2016-09-30
申请人： Intel Corporation
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/38 , G06F9/30 , G06F11/07 , G06F9/54 , G06F12/0875
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.

7. 发明授权

US09367116B2 Apparatus to reduce idle link power in a platform 有权
标题翻译：降低平台空闲链路功率的装置
公开(公告)号：US09367116B2
公开(公告)日：2016-06-14
申请号：US14978340
申请日：2015-12-22
申请人： Intel Corporation
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.
摘要翻译：提供了一种芯片系统（SoC），包括处理核心和根系统。事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测电路被禁用，并且不保持共模电压。根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

8. 发明授权

US09280198B2 Method and apparatus to reduce idle link power in a platform 有权
标题翻译：降低平台空闲链路功率的方法和装置
公开(公告)号：US09280198B2
公开(公告)日：2016-03-08
申请号：US14148530
申请日：2014-01-06
申请人： Intel Corporation
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译：一种降低平台空闲链路功率的方法和装置。在本发明的一个实施例中，主机及其在平台中的耦合端点各自具有低功率空闲链路状态，其允许在主机及其耦合的端点中禁用高速链路电路。这允许平台减少其空闲功率，因为在本发明的一个实施例中，主机及其耦合端点能够关闭其高速链路电路。

9. 发明授权

US09026682B2 Prefectching in PCI express 有权
标题翻译：预防PCI Express
公开(公告)号：US09026682B2
公开(公告)日：2015-05-05
申请号：US13713635
申请日：2012-12-13
申请人： Intel Corporation
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F12/08 , G06F1/32 , H04L12/66 , G06F13/40 , G06F13/38 , G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

10. 发明申请

US20140310543A1 METHOD AND APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM 审中-公开
标题翻译：减少平台中空闲链路功率的方法和设备
公开(公告)号：US20140310543A1
公开(公告)日：2014-10-16
申请号：US14148530
申请日：2014-01-06
申请人： Intel Corporation
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsake , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译：一种降低平台空闲链路功率的方法和装置。在本发明的一个实施例中，主机及其在平台中的耦合端点各自具有低功率空闲链路状态，其允许在主机及其耦合的端点中禁用高速链路电路。这允许平台减少其空闲功率，因为在本发明的一个实施例中，主机及其耦合端点能够关闭其高速链路电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式