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1. 发明授权

US09734079B2 Hybrid exclusive multi-level memory architecture with memory management 有权
公开(公告)号：US09734079B2
公开(公告)日：2017-08-15
申请号：US13931701
申请日：2013-06-28
申请人： Intel Corporation
发明人： Dannie G. Feekes , Shlomo Raikin , Blaise Fanning , Joydeep Ray , Julius Mandelblat , Ariel Berkovits , Eran Shifer , Zvika Greenfield , Evgeny Bolotin
IPC分类号： G06F12/00 , G06F12/0893 , G06F12/08 , G06F12/0866 , G06F12/06 , G06F1/32
CPC分类号： G06F12/0893 , G06F1/32 , G06F1/3275 , G06F12/063 , G06F12/08 , G06F12/0866 , G06F2212/205 , G06F2212/206 , G06F2212/281 , G06F2212/604 , G06F2212/608 , Y02D10/13 , Y02D10/14
摘要： Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

2. 发明授权

US10901748B2 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions 有权
公开(公告)号：US10901748B2
公开(公告)日：2021-01-26
申请号：US16149050
申请日：2018-10-01
申请人： Intel Corporation
发明人： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80
摘要： An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

3. 发明申请

US20180285261A1 DYNAMIC FILL POLICY FOR A SHARED CACHE 审中-公开
公开(公告)号：US20180285261A1
公开(公告)日：2018-10-04
申请号：US15476816
申请日：2017-03-31
申请人： Intel Corporation
发明人： Ayan Mandal , Eran Shifer , Leon Polishuk
IPC分类号： G06F12/084 , G06F12/0846 , G06F12/0855 , G06F9/50 , G06F12/02 , G06F12/0888 , G06F12/1027 , G06F3/06
CPC分类号： G06F12/084 , G06F3/0653 , G06F9/5016 , G06F12/0223 , G06F12/0846 , G06F12/0855 , G06F12/0888 , G06F12/1027 , G06F2212/1028 , G06F2212/1044 , G06F2212/604 , G06F2212/6046
摘要： Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

4. 发明授权

US09582287B2 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions 有权
标题翻译：处理器具有多个核心，共享核心扩展逻辑和共享核心扩展利用指令
公开(公告)号：US09582287B2
公开(公告)日：2017-02-28
申请号：US13629460
申请日：2012-09-27
申请人： Intel Corporation
发明人： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3887 , G06F9/30076 , G06F9/3879 , G06F15/8007
摘要： An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.
摘要翻译：一个方面的装置包括与多个核心中的每一个耦合的多个核心和共享核心扩展逻辑。共享核心扩展逻辑具有由多个核心中的每一个共享的共享数据处理逻辑。用于响应于共享核心扩展调用指令的每个核心的指令执行逻辑是调用共享的核心扩展逻辑。呼叫是由共享数据处理逻辑代表相应的核进行数据处理。还公开了其他装置，方法和系统。

5. 发明授权

US10229059B2 Dynamic fill policy for a shared cache 有权
公开(公告)号：US10229059B2
公开(公告)日：2019-03-12
申请号：US15476816
申请日：2017-03-31
申请人： Intel Corporation
发明人： Ayan Mandal , Eran Shifer , Leon Polishuk
IPC分类号： G06F12/08 , G06F12/084 , G06F12/0846 , G06F12/0855 , G06F9/50 , G06F12/02 , G06F12/0888 , G06F12/1027 , G06F3/06 , G06F9/455
摘要： Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

6. 发明授权

US12086603B2 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions 有权
公开(公告)号：US12086603B2
公开(公告)日：2024-09-10
申请号：US17975596
申请日：2022-10-27
申请人： Intel Corporation
发明人： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/30076 , G06F9/3879 , G06F15/8007
摘要： An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

7. 发明申请

US20180173637A1 EFFICIENT MEMORY AWARE CACHE MANAGEMENT 审中-公开
公开(公告)号：US20180173637A1
公开(公告)日：2018-06-21
申请号：US15387429
申请日：2016-12-21
申请人： Intel Corporation
发明人： Eran Shifer , Ravi K. Venkatesan , Leon Polishuk , Anant V. Nori , Ori Lempel , Manikantan R
IPC分类号： G06F12/0891 , G06F12/0815
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F12/0862 , G06F12/0866 , G06F2212/1024 , G06F2212/62
摘要： An indication of a first cache entry to be removed from a cache, the first cache entry corresponding to a first memory address in a memory may be received. A second memory address in the memory based at least in part on the first memory address may be identified. A request to identify a second cache entry in the cache corresponding to the second memory address and to determine whether a removal policy is satisfied may be sent. A response to the request, the response comprising an indication of the second cache entry to be removed from the cache based at least in part on the request may be sent. The first cache entry and the second cache entry from the cache may be removed. Data corresponding to the first and second cache entries to the memory with a single page file access may be written.

8. 发明授权

US11494194B2 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions 有权
公开(公告)号：US11494194B2
公开(公告)日：2022-11-08
申请号：US17216618
申请日：2021-03-29
申请人： Intel Corporation
发明人： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80
摘要： An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

9. 发明授权

US10963263B2 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions 有权
公开(公告)号：US10963263B2
公开(公告)日：2021-03-30
申请号：US16059001
申请日：2018-08-08
申请人： Intel Corporation
发明人： Eran Shifer , Mostafa Hagog , Eliyahu Turiel
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80
摘要： An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

10. 发明授权

US10599568B2 Management of coherent links and multi-level memory 有权
公开(公告)号：US10599568B2
公开(公告)日：2020-03-24
申请号：US15948569
申请日：2018-04-09
申请人： Intel Corporation
发明人： Eran Shifer
IPC分类号： G06F12/0815 , G06F12/084 , G06F12/123 , G06F12/1009 , G06F12/0831 , G06F12/1027
摘要： Techniques for managing multi-level memory and coherency using a unified page granular controller can simplify software programming of both file system handling for persistent memory and parallel programming of host and accelerator and enable better software utilization of host processors and accelerators. As part of the management techniques, a line granular controller cooperates with a page granular controller to support both fine grain and coarse grain coherency and maintain overall system inclusion property. In one example, a controller to manage coherency in a system includes a memory data structure and on-die tag cache to store state information to indicate locations of pages in a memory hierarchy and an ownership state for the pages, the ownership state indicating whether the pages are owned by a host processor, owned by an accelerator device, or shared by the host processor and the accelerator device. The controller can also include logic to, in response to a memory access request from the host processor or the accelerator to access a cacheline in a page in a state indicating ownership by a device other than the requesting device, cause the page to transition to a state in which the requesting device owns or shares the page.

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