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1. 发明申请

US20190102537A1 TECHNOLOGIES FOR UNTRUSTED CODE EXECUTION WITH PROCESSOR SANDBOX SUPPORT 审中-公开
公开(公告)号：US20190102537A1
公开(公告)日：2019-04-04
申请号：US15720083
申请日：2017-09-29
申请人： Intel Corporation
发明人： Mingwei Zhang , Mingqiu Sun , Ravi L. Sahita , Chunhui Zhang , Xiaoning Li
IPC分类号： G06F21/53 , G06F21/12 , G06F9/38 , G06F9/45
摘要： Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

2. 发明授权

US11106599B2 System and method for replacement in associative memories using weighted PLRU trees 有权
公开(公告)号：US11106599B2
公开(公告)日：2021-08-31
申请号：US16370919
申请日：2019-03-30
申请人： Intel Corporation
发明人： Chunhui Zhang , Robert S. Chappell , Yury N. Ilin
IPC分类号： G06F12/08 , G06F12/123 , G06N7/00 , G06F9/30 , G06F16/901 , G06F12/0846
摘要： A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.

3. 发明申请

US20190227948A1 SYSTEM AND METHOD FOR REPLACEMENT IN ASSOCIATIVE MEMORIES USING WEIGHTED PLRU TREES 审中-公开
公开(公告)号：US20190227948A1
公开(公告)日：2019-07-25
申请号：US16370919
申请日：2019-03-30
申请人： Intel Corporation
发明人： Chunhui Zhang , Robert S. Chappell , Yury N. Ilin
IPC分类号： G06F12/123 , G06N7/00 , G06F12/0846 , G06F16/901 , G06F9/30
摘要： A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.

4. 发明申请

US20170031729A1 Generational Thread Scheduler 审中-公开
标题翻译：生成线程调度程序
公开(公告)号：US20170031729A1
公开(公告)日：2017-02-02
申请号：US15290375
申请日：2016-10-11
申请人： Intel Corporation
发明人： Edward T. Grochowski , Michael D. Upton , George Z. Chrysos , Chunhui Zhang , Mohammed L. Al-Aqrabawi
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F2209/5014
摘要： Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.
摘要翻译：这里公开的是一代代线程调度器。一个实施例可以与处理器多线程逻辑一起使用以执行可执行指令的线程，以及在竞争访问共享资源的可执行指令的线程之间公平分配的共享资源。生成线程调度逻辑可以通过向共享资源授予对共享资源的预留的第一请求线程访问来对其执行线程的请求线程，然后阻止第一线程重新请求共享资源，直到已分配了预留的每个其他线程已被授予对共享资源的访问权限。当分配了预约的生成的每个请求线程已经满足了请求时，可以清除生成跟踪状态。

5. 发明授权

US11055401B2 Technologies for untrusted code execution with processor sandbox support 有权
公开(公告)号：US11055401B2
公开(公告)日：2021-07-06
申请号：US15720083
申请日：2017-09-29
申请人： Intel Corporation
发明人： Mingwei Zhang , Mingqiu Sun , Ravi L. Sahita , Chunhui Zhang , Xiaoning Li
IPC分类号： H04L29/00 , G06F21/53 , G06F8/41 , G06F9/38 , G06F21/12
摘要： Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

6. 发明授权

US10379864B2 Processor prefetch throttling based on short streams 有权
公开(公告)号：US10379864B2
公开(公告)日：2019-08-13
申请号：US15390588
申请日：2016-12-26
申请人： Intel Corporation
发明人： Chunhui Zhang , Seth H. Pugsley , Mark J. Dechene
IPC分类号： G06F9/305 , G06F9/34 , G06F12/08 , G06F9/38 , G06F9/345 , G06F9/30 , G06F9/355 , G06F12/0862
摘要： In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.

7. 发明授权

US10261904B2 Memory sequencing with coherent and non-coherent sub-systems 有权
公开(公告)号：US10261904B2
公开(公告)日：2019-04-16
申请号：US15835384
申请日：2017-12-07
申请人： Intel Corporation
发明人： Chunhui Zhang , George Z. Chrysos , Edward T. Grochowski , Ramacharan Sundararaman , Chung-Lun Chan , Federico Ardanaz
IPC分类号： G06F9/38 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/0831 , G06F12/0842
摘要： Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

8. 发明授权

US11068399B2 Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache line 有权
公开(公告)号：US11068399B2
公开(公告)日：2021-07-20
申请号：US15720379
申请日：2017-09-29
申请人： Intel Corporation
发明人： Bin Li , Chunhui Zhang , Ren Wang , Ram Huggahalli
IPC分类号： G06F12/00 , G06F12/0831 , G06F9/30 , G06F9/46 , H04L12/933 , H04L12/741 , H04L12/861
摘要： Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which is configured to receive a network packet, write the payload of the network packet to a data storage device of the target computing device, and obtain, subsequent to having transmitted a last write request to write the payload to the data storage device, ownership of a flag cache line of a cache of the target computing device. The NIC is additionally configured to receive a snoop request from a processor of the target computing device, identify whether the received snoop request corresponds to a read flag snoop request associated with an active request being processed by the NIC, and hold the received snoop request for delayed return in response to having identified the received snoop request as the read flag snoop request. Other embodiments are described herein.

9. 发明申请

US20200233664A1 EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE 审中-公开
公开(公告)号：US20200233664A1
公开(公告)日：2020-07-23
申请号：US16717258
申请日：2019-12-17
申请人： Intel Corporation
发明人： Ren Wang , Chunhui Zhang , Qixiong J. Bian , Bret L. Toll , Jason W. Brandt
IPC分类号： G06F9/30 , G06F12/128 , G06F12/0804 , G06F9/38 , G06F12/0811 , G06F13/28 , G06F12/0891 , G06F12/0875 , G06F12/0842
摘要： Method and apparatus for efficient range-based memory writeback is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.

10. 发明申请

US20190102301A1 TECHNOLOGIES FOR ENFORCING COHERENCE ORDERING IN CONSUMER POLLING INTERACTIONS 审中-公开
公开(公告)号：US20190102301A1
公开(公告)日：2019-04-04
申请号：US15720379
申请日：2017-09-29
申请人： Intel Corporation
发明人： Bin Li , Chunhui Zhang , Ren Wang , Ram Huggahalli
IPC分类号： G06F12/0831 , G06F9/30 , G06F9/46 , H04L12/741 , H04L12/933
摘要： Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which is configured to receive a network packet, write the payload of the network packet to a data storage device of the target computing device, and obtain, subsequent to having transmitted a last write request to write the payload to the data storage device, ownership of a flag cache line of a cache of the target computing device. The NIC is additionally configured to receive a snoop request from a processor of the target computing device, identify whether the received snoop request corresponds to a read flag snoop request associated with an active request being processed by the NIC, and hold the received snoop request for delayed return in response to having identified the received snoop request as the read flag snoop request. Other embodiments are described herein.

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