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1. 发明授权

US10797855B2 Signal detection techniques using clock data recovery 有权
公开(公告)号：US10797855B2
公开(公告)日：2020-10-06
申请号：US16036227
申请日：2018-07-16
申请人： INTEL CORPORATION
发明人： Amir Laufer , Itamar Levin , Kevan A. Lillie
IPC分类号： H04L7/04 , H03L7/08 , H03L7/091 , H04L7/00 , H04L7/033
摘要： Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

2. 发明公开

US20240020256A1 COMPONENT FIRMWARE INTERACTION USING HARDWARE REGISTERS 审中-公开
公开(公告)号：US20240020256A1
公开(公告)日：2024-01-18
申请号：US18375054
申请日：2023-09-29
申请人： Intel Corporation
发明人： Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC分类号： G06F13/38 , G06F13/16 , G06F13/20 , G06F9/4401 , G06F30/18
CPC分类号： G06F13/382 , G06F13/16 , G06F13/20 , G06F9/4411 , G06F30/18 , G06F2213/0026 , G06F2213/0024
摘要： Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

3. 发明授权

US10027470B1 Signal detection techniques using clock data recovery 有权
公开(公告)号：US10027470B1
公开(公告)日：2018-07-17
申请号：US15393186
申请日：2016-12-28
申请人： INTEL CORPORATION
发明人： Amir Laufer , Itamar Levin , Kevan A. Lillie
IPC分类号： H04L7/04 , H04L7/00 , H03L7/08
摘要： Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

4. 发明授权

US11809353B2 Component firmware interaction using hardware registers 有权
公开(公告)号：US11809353B2
公开(公告)日：2023-11-07
申请号：US15476936
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： Kevan A. Lillie , Shlomi Lalush , Yaakov Dalsace , Adee Ofir Ran , Assaf Benhamou , David Golodni , Itay Tamir , Amir Laufer
IPC分类号： G06F13/20 , G06F13/38 , G06F13/16 , G06F9/4401 , G06F30/18
CPC分类号： G06F13/382 , G06F9/4411 , G06F13/16 , G06F13/20 , G06F30/18 , G06F2213/0024 , G06F2213/0026
摘要： Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

5. 发明授权

US09917685B2 Eye width measurement and margining in communication systems 有权
公开(公告)号：US09917685B2
公开(公告)日：2018-03-13
申请号：US15614470
申请日：2017-06-05
申请人： Intel Corporation
发明人： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
IPC分类号： H04L7/00 , H04L1/00 , H03L7/107 , H03L7/093 , H03L7/08 , H04L1/20 , H04L1/24
CPC分类号： H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
摘要： Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

6. 发明授权

US09215061B2 Eye width measurement and margining in communication systems 有权
标题翻译：通信系统的眼宽测量和边缘
公开(公告)号：US09215061B2
公开(公告)日：2015-12-15
申请号：US14667146
申请日：2015-03-24
申请人： Intel Corporation
发明人： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
IPC分类号： H04L7/00 , H04L1/00 , H03L7/08 , H03L7/093 , H03L7/107
CPC分类号： H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
摘要： Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.
摘要翻译：通常，本公开描述了通信系统中的眼宽测量和边缘化。一种装置可以被配置为：响应于将边缘化时钟信号同步到接收机时钟信号，将相位检测器与被测接收机的CDR环路滤波器分离; 对环路滤波器施加裕度输入，边缘输入被配置为将边缘化时钟信号的频率移动与边界输入相关的恒定量; 比较第一比特流和第二比特流，并配置为检测与发送的比特流相关的第一比特流的错误; 以及接收机时钟信号或边缘时钟信号的计数周期，其中与被测接收机相关联的眼睛宽度与边缘输入，接收机时钟信号的频率以及当检测到错误时的时钟周期的计数有关。

7. 发明授权

US09680668B2 Delay resilient decision feedback equalizer 有权
公开(公告)号：US09680668B2
公开(公告)日：2017-06-13
申请号：US14572756
申请日：2014-12-16
申请人： Intel Corporation
发明人： Amir Laufer , Itamar Levin
IPC分类号： H03K5/159 , H04L25/03
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03579
摘要： Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.

8. 发明授权

US09673966B2 Eye width measurement and margining in communication systems 有权
公开(公告)号：US09673966B2
公开(公告)日：2017-06-06
申请号：US14968616
申请日：2015-12-14
申请人： Intel Corporation
发明人： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
IPC分类号： H04L7/00 , H04L1/00 , H03L7/08 , H03L7/093 , H03L7/107 , H04L1/20 , H04L1/24
CPC分类号： H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
摘要： Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

9. 发明申请

US20160173300A1 DELAY RESILIENT DECISION FEEDBACK EQUALIZER 有权
标题翻译：延迟回馈决策反馈平均
公开(公告)号：US20160173300A1
公开(公告)日：2016-06-16
申请号：US14572756
申请日：2014-12-16
申请人： Intel Corporation
发明人： Amir Laufer , Itamar Levin
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03579
摘要： Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.
摘要翻译：描述了一种装置，其包括具有第一DFE抽头路径和非第一DFE抽头路径的判决反馈均衡器（DFE），其中DFE在非第一DFE抽头路径的信号路径中包括可变延迟电路。在一些实施例中，提供一种装置，包括：一个夏天; 从夏天接收输入的切片机; 第一反馈回路，用于取消第一后视标，所述第一反馈回路通过将所述切片机耦合到所述夏季而形成回路; 以及用于消除第二后置光标的第二反馈回路，所述第二反馈回路通过将所述第一反馈回路的输入耦合到所述加法器来形成回路，其中所述第二反馈回路在其输入处具有可编程延迟。

10. 发明授权

US08989329B2 Eye width measurement and margining in communication systems 有权
公开(公告)号：US08989329B2
公开(公告)日：2015-03-24
申请号：US13836383
申请日：2013-03-15
申请人： Intel Corporation
发明人： Dima Hammad , Vadim Levin , Amir Laufer , Ron Bar-Lev , Noam Familia , Itamar Levin
IPC分类号： H04L7/00
CPC分类号： H04L7/0054 , H03L7/0807 , H03L7/093 , H03L7/1075 , H04L1/00 , H04L1/203 , H04L1/24 , H04L7/0016 , H04L7/0062 , H04L7/0079
摘要： Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

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