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1. 发明授权

US10157956B2 Method of monolithic integration of hyperspectral image sensor 有权
公开(公告)号：US10157956B2
公开(公告)日：2018-12-18
申请号：US15477191
申请日：2017-04-03
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Hushan Cui , Jinjuan Xiang , Xiaobin He , Tao Yang , Junfeng Li , Chao Zhao
IPC分类号： H01L21/00 , H01L27/146 , H01L31/0216 , H01L31/0232
摘要： A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m≥1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

2. 发明授权

US09306016B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09306016B2
公开(公告)日：2016-04-05
申请号：US14423395
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/00 , H01L29/00 , H01L29/417 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/78 , H01L29/165
CPC分类号： H01L29/41783 , H01L21/02181 , H01L21/02192 , H01L21/02194 , H01L21/30604 , H01L21/31111 , H01L21/31116 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/66825 , H01L29/7848 , H01L29/78654
摘要： The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device. The present invention is capable of eliminating pathway for leakage current between source/drain regions and SOI substrate at the meantime of reducing contact resistance at source/drain regions.
摘要翻译：本发明提供一种制造半导体器件的方法，其包括：提供SOI衬底，其包括基底层，位于基底层上的绝缘层和位于绝缘层上的有源层; 在SOI衬底上形成栅叠层; 用栅极叠层作为掩模蚀刻有源层，绝缘层和SOI衬底的基底层的一部分，以在栅叠层的两侧形成沟槽; 在所述沟槽内形成晶体介质层，其中所述晶体介质层的上表面低于所述绝缘层的上表面，并且不低于所述绝缘层的下表面; 并在晶体介质层上形成源/漏区。本发明还提供一种半导体器件。本发明能够消除源极/漏极区域和SOI衬底之间的泄漏电流的途径，同时降低源极/漏极区域的接触电阻。

3. 发明申请

US20150287606A1 METHOD OF DEPOSITING TUNGSTEN LAYER WITH IMPROVED ADHESION AND FILLING BEHAVIOR 有权
标题翻译：具有改善粘合和填充行为的沉积层的方法
公开(公告)号：US20150287606A1
公开(公告)日：2015-10-08
申请号：US14744835
申请日：2015-06-19
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Qiang Xu , Chao Zhao , Jun Luo , Guilei Wang , Tao Yang , Junfeng Li
IPC分类号： H01L21/285 , H01L21/28
CPC分类号： H01L21/28562 , C23C16/0272 , C23C16/14 , C23C16/45525 , H01L21/28079 , H01L21/28088 , H01L21/32051 , H01L21/76876 , H01L21/76877 , H01L29/66545
摘要： A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.
摘要翻译：公开了沉积钨（W）层的方法。一方面，该方法包括在衬底的表面上沉积SiH 4基底W膜以预处理该表面。该方法包括在预处理的表面上沉积B2H6基底W层。 SiH4基底W膜可以是几个原子层厚。膜和基底W层可以沉积在单个ALD工艺中，包括反应气体浸泡，反应气体引入和主沉积操作。形成膜可以包括在气体浸泡操作期间将SiH 4气体引入反应腔中，并且在气体引入操作期间将SiH 4和WF 6气体引入空腔。 SiH4和WF6气体可以根据待沉积的钨层的厚度交替地引入多个循环。

4. 发明申请

US20140273426A1 Method for Manufacturing Dummy Gate in Gate-Last Process and Dummy Gate in Gate-Last Process 有权
标题翻译：闸门最后过程中虚拟门制造方法及闸门最后过程中虚拟门的制作方法
公开(公告)号：US20140273426A1
公开(公告)日：2014-09-18
申请号：US14119869
申请日：2012-12-12
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Chao Zhao
IPC分类号： H01L29/51
CPC分类号： H01L21/28123 , H01L21/32139 , H01L29/513 , H01L29/66545
摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.
摘要翻译：提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层，并修剪硬掩模层，使得修整的硬掩模层具有小于或等于22nm的宽度; 并根据修整的硬掩模层蚀刻顶层非晶硅，ONO结构的硬掩模和底层非晶硅，以及去除硬掩模层和顶层非晶硅。

5. 发明申请

US20190157345A1 MRAM, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE MRAM 审中-公开
公开(公告)号：US20190157345A1
公开(公告)日：2019-05-23
申请号：US16177999
申请日：2018-11-01
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong ZHU , Junjie Li , Chao Zhao
IPC分类号： H01L27/22 , H01L43/12 , H01L43/02
摘要： A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

6. 发明授权

US10276366B2 Low interface state device and method for manufacturing the same 有权
公开(公告)号：US10276366B2
公开(公告)日：2019-04-30
申请号：US14821203
申请日：2015-08-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Xinyu Liu , Sen Huang , Xinhua Wang , Ke Wei , Wenwu Wang , Junfeng Li , Chao Zhao
IPC分类号： H01L21/02 , C23C16/02 , C23C16/30
摘要： A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

7. 发明申请

US20150279745A1 METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150279745A1
公开(公告)日：2015-10-01
申请号：US14233320
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Huilong Zhu , Gaobo Xu , Huajie Zhou , Qingqing Liang , Dapeng Chen , Chao Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.
摘要翻译：公开了一种用于制造半导体器件的方法，该半导体器件包括形成在一个半导体衬底上的两种相反类型的MOSFET，该方法包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的所述部分包括位于半导体衬底，位于源极/漏极区域之间以及半导体衬底之上的虚拟栅极堆叠以及围绕伪栅极堆叠的栅极间隔区; 去除所述MOSFET的虚拟栅极堆叠以形成暴露所述半导体衬底的表面的栅极开口; 在所述半导体结构的暴露表面上形成界面氧化物层; 在栅极开口内的界面氧化物层上形成高K栅电介质; 在高K栅极电介质上形成第一金属栅极层; 在第一金属栅极层中注入掺杂离子; 在所述第一金属栅极层上形成第二金属栅极层以填充所述栅极开口; 以及退火以在所述高K栅极电介质和所述第一金属栅极层之间的上界面处以及所述高K栅极电介质和所述界面氧化物之间的下界面处扩散和积累所述掺杂离子，并且在所述高K栅极电介质和所述界面氧化物之间产生电偶极子通过界面反应在高K栅极电介质和界面氧化物之间降低界面。

8. 发明申请

US20150214332A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150214332A1
公开(公告)日：2015-07-30
申请号：US14426690
申请日：2012-11-13
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Chunlong Li , Junfeng Li , Jiang Yan , Lingkuan Meng , Xiaobin He , Guanglu Chen , Chao Zhao
IPC分类号： H01L29/66 , H01L29/51 , H01L21/3105
CPC分类号： H01L29/66545 , H01L21/31055 , H01L21/31144 , H01L21/32139 , H01L29/51 , H01L29/66492 , H01L29/66621 , H01L29/66833
摘要： A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.
摘要翻译：一种用于制造虚拟栅极结构的方法。该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。

9. 发明授权

US11127783B2 MRAM, method of manufacturing the same, and electronic device including the MRAM 有权
公开(公告)号：US11127783B2
公开(公告)日：2021-09-21
申请号：US16177999
申请日：2018-11-01
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Junjie Li , Chao Zhao
IPC分类号： H01L27/22 , H01L43/02 , H01L43/12 , H01L43/10
摘要： A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

10. 发明授权

US10141408B2 Method and arrangement for reducing contact resistance of two-dimensional crystal material 有权
公开(公告)号：US10141408B2
公开(公告)日：2018-11-27
申请号：US14651980
申请日：2014-03-18
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Kunpeng Jia , Yajuan Su , Huilong Zhu , Chao Zhao
IPC分类号： H01L21/04 , H01L29/16 , H01L29/24 , H01L29/167 , H01L21/265 , H01L21/266 , H01L21/283 , H01L29/45 , H01L21/426 , H01L21/441 , H01L21/477 , H01L21/324 , H01L21/285
摘要： A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.

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