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1. 发明申请

US20060006552A1 Bond pad structure for copper metallization having increased reliability and method for fabricating same 有权
标题翻译：用于铜金属化的焊盘结构具有增加的可靠性及其制造方法
公开(公告)号：US20060006552A1
公开(公告)日：2006-01-12
申请号：US10887585
申请日：2004-07-08
申请人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon Chan , Cinti Chen
发明人： Inkuk Kang , Hiroyuki Kinoshita , Boon-Yong Ang , Hajime Wada , Simon Chan , Cinti Chen
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05073 , H01L2224/05147 , H01L2224/05181 , H01L2224/05554 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042
摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.
摘要翻译：根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。该结构还包括位于金属焊盘上的层间电介质层。该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。端子通孔仅沿着金属焊盘的一侧延伸。该结构还包括位于层间电介质层和端子通孔中的端子金属层。所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

2. 发明申请

US20080153269A1 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US20080153269A1
公开(公告)日：2008-06-26
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.
摘要翻译：本发明涉及在形成存储器件时实现虚拟瓦片的系统和方法。该系统和方法包括在半导体衬底上形成存储芯阵列的至少一部分，包括：在衬底中形成STI结构，在衬底上沉积氧化层，在氧化物层上形成第一多晶硅层，掺杂第一多晶硅层，在第一多晶硅层上形成第二多晶硅层，图案化至少一个存储器芯，图案化至少一个虚拟贴片并执行后端处理。

3. 发明授权

US07977218B2 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US07977218B2
公开(公告)日：2011-07-12
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.
摘要翻译：新颖的制造方法实现使用虚拟瓦片以避免在形成存储器件区域区域中的在线充电，ESD事件和这种电荷效应的影响。一种方法包括在半导体衬底上形成至少一部分存储器芯阵列，该半导体衬底涉及在衬底中形成基本上围绕阵列内的存储器件区域区域的STI结构。在存储器件区域和STI之上的衬底上形成氧化物层，其中形成在存储器件区域上的氧化物层的内部部分比在STI上形成的氧化物层的外部部分更厚。然后在内部和外部部分上形成第一多晶硅层，包括形成在一个或多个外部部分上并且电连接到至少一个内部部分的一个或多个虚拟瓦片。

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