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2. 发明授权

US07208378B2 Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 失效
标题翻译：具有多个栅极氧化物层的半导体器件及其制造方法
公开(公告)号：US07208378B2
公开(公告)日：2007-04-24
申请号：US11126944
申请日：2005-05-10
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.
摘要翻译：制造半导体器件的方法包括在衬底上限定第一电压区域，第二电压区域和第三电压区域。第一，第二和第三电压区域被配置为分别处理彼此不同的第一，第二和第三电压电平。形成覆盖第一，第二和第三电压区域的氮化物层。形成覆盖氮化物层的氧化物层。图案化氧化物层以暴露覆盖第一电压区域的氮化物层的一部分。使用湿蚀刻工艺去除氮化物层的暴露部分。形成覆盖第一电压区域的第一栅极氧化物层。除去覆盖第二和第三电压区域的氧化物层和氮化物层的部分。杂质被选择性地注入到第三电压区域中，同时防止在第二电压区域中提供杂质。覆盖第二电压区域的第二栅极氧化物和覆盖第三电压区域的第三栅极氧化物同时形成。第二栅极氧化物比第三栅极氧化物厚。

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