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1. 发明申请

US20160254367A1 ELECTRODE-ALIGNED SELECTIVE EPITAXY METHOD FOR VERTICAL POWER DEVICES 有权
标题翻译：用于垂直功率器件的电极对准的选择性外延方法
公开(公告)号：US20160254367A1
公开(公告)日：2016-09-01
申请号：US14633359
申请日：2015-02-27
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Oliver Blank , Rudolf Rothmaler , Johannes Baumgartl
IPC分类号： H01L29/66 , H01L29/49 , H01L21/02
CPC分类号： H01L29/66666 , H01L21/02238 , H01L21/02255 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L29/4916 , H01L29/66545
摘要： A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.
摘要翻译：一种形成沟槽电极结构的方法包括：在半导体衬底上形成第一介电层，在第一介电层上方形成第二层，并形成一个延伸穿过第二层和第一介质层到半导体衬底的开口，未覆盖半导体衬底。该方法还包括在半导体衬底的未覆盖部分上形成外延层，在形成外延层之后去除第二层，并用导电材料填充通过去除第二层形成的开放空间。导电材料形成由外延层横向包围的电极。

2. 发明授权

US09425788B1 Current sensors and methods of improving accuracy thereof 有权
标题翻译：电流传感器和提高精度的方法
公开(公告)号：US09425788B1
公开(公告)日：2016-08-23
申请号：US14661960
申请日：2015-03-18
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Oliver Blank , Quaglino Roberto
IPC分类号： H03K5/003 , H03K17/687 , H01L27/088 , H01L29/40
CPC分类号： H01L29/402 , H01L24/16 , H01L24/40 , H01L24/48 , H01L29/2003 , H01L29/7815 , H01L29/7835 , H01L2224/16245 , H01L2224/40245 , H01L2224/48247 , H01L2224/48464 , H01L2224/73221 , H01L2924/00014 , H01L2924/181 , H03K2217/0027 , H01L2924/00012 , H01L2224/37099 , H01L2224/45099 , H01L2224/13099 , H01L2224/05599
摘要： A method for operating a circuit includes providing a three terminal main transistor and a four terminal sense transistor having a field plate. The method includes simultaneously applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor, and applying a field plate pulse on a field plate of the sense transistor. The field plate pulse is synchronous and in phase with the gate pulse.
摘要翻译：一种用于操作电路的方法包括提供三端主晶体管和具有场板的四端检测晶体管。该方法包括同时将栅极脉冲施加在感测晶体管的栅极端子和主晶体管的栅极端子上，并将场板脉冲施加在感测晶体管的场板上。场板脉冲是同步的，与栅极脉冲同相。

3. 发明申请

US20160372538A1 Method of Manufacturing a Semiconductor Device Having a Charge Compensation Region Underneath a Gate Trench 审中-公开
标题翻译：在栅极沟槽下方具有充电补偿区域的半导体器件的制造方法
公开(公告)号：US20160372538A1
公开(公告)日：2016-12-22
申请号：US15251606
申请日：2016-08-30
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Li Juin Yip , Oliver Blank , Martin Vielemeyer , Franz Hirler
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/66 , H01L29/40
CPC分类号： H01L29/063 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/401 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.
摘要翻译：提供一种形成半导体器件的方法。该器件包括具有主表面和与主表面垂直间隔开的后表面的半导体衬底，第一掺杂区，第二掺杂区和第三掺杂区。第三掺杂区域介于主表面下方的第一和第二掺杂区域之间。具有场板的场板沟槽从主表面垂直延伸到布置在第一掺杂区域中的底部。具有栅电极的栅极沟槽从主表面垂直延伸到第一掺杂区域。补偿区域从栅极沟槽的底部垂直地延伸到第一掺杂区域。补偿区域与栅极沟槽横向对齐，并且沿着平行于主表面的器件的横截面平面邻近场板。

4. 发明授权

US09443973B2 Semiconductor device with charge compensation region underneath gate trench 有权
标题翻译：具有栅极沟槽下方的电荷补偿区域的半导体器件
公开(公告)号：US09443973B2
公开(公告)日：2016-09-13
申请号：US14554193
申请日：2014-11-26
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Li Juin Yip , Oliver Blank , Martin Vielemeyer , Franz Hirler
IPC分类号： H01L29/76 , H01L29/78 , H01L29/06 , H01L29/40 , H01L29/66 , H01L21/306 , H01L21/308 , H01L21/266
CPC分类号： H01L29/063 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/401 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.
摘要翻译：半导体衬底具有与主表面垂直间隔开的主表面和后表面，第一掺杂区，第二掺杂区和第三掺杂区。第三掺杂区域介于主表面下方的第一和第二掺杂区域之间。具有场板的场板沟槽从主表面垂直延伸到布置在第一掺杂区域中的底部。具有栅电极的栅极沟槽从主表面垂直延伸到第一掺杂区域。补偿区域从栅极沟槽的底部垂直地延伸到第一掺杂区域。补偿区域与栅极沟槽横向对齐，并且沿着平行于主表面的器件的横截面平面邻近场板。

5. 发明申请

US20150349056A1 SEMICONDUCTOR DEVICE COMPRISING TRENCH STRUCTURES 有权
标题翻译：包含TRENCH结构的半导体器件
公开(公告)号：US20150349056A1
公开(公告)日：2015-12-03
申请号：US14293479
申请日：2014-06-02
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Rudolf Rothmaler , Oliver Blank , Joerg Ortner
IPC分类号： H01L29/06 , H01L29/78 , H01L29/423
CPC分类号： H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.
摘要翻译：半导体器件包括在中心部分之外的中心部分和边缘终止部分。中心部分包括在半导体衬底中的晶体管单元阵列。晶体管单元阵列的晶体管单元的组件设置在半导体衬底中的相邻沟槽结构中。沟槽结构沿平行于半导体衬底的主表面的第一线性方向延伸。沟槽结构包括在平行于中心部分中的主表面的平面中的多个级联沟槽段，至少一个沟槽段连接一个沟槽结构的第一点和第二点，第一点和第二点沿着第一线性方向布置。沟槽段包括沿与第一方向不同的方向延伸的部分。

6. 发明授权

US10199456B2 Method of manufacturing a semiconductor device having a charge compensation region underneath a gate trench 有权
公开(公告)号：US10199456B2
公开(公告)日：2019-02-05
申请号：US15251606
申请日：2016-08-30
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Li Juin Yip , Oliver Blank , Martin Vielemeyer , Franz Hirler
IPC分类号： H01L29/78 , H01L29/40 , H01L29/66 , H01L29/06 , H01L21/306 , H01L21/308 , H01L21/266 , H01L21/265 , H01L29/10 , H01L29/739
摘要： A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

7. 发明授权

US09496339B2 Semiconductor device comprising trench structures 有权
标题翻译：包括沟槽结构的半导体器件
公开(公告)号：US09496339B2
公开(公告)日：2016-11-15
申请号：US14293479
申请日：2014-06-02
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Rudolf Rothmaler , Oliver Blank , Joerg Ortner
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/40
CPC分类号： H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.
摘要翻译：半导体器件包括在中心部分之外的中心部分和边缘终止部分。中心部分包括在半导体衬底中的晶体管单元阵列。晶体管单元阵列的晶体管单元的组件设置在半导体衬底中的相邻沟槽结构中。沟槽结构沿平行于半导体衬底的主表面的第一线性方向延伸。沟槽结构包括在平行于中心部分中的主表面的平面中的多个级联沟槽段，至少一个沟槽段连接一个沟槽结构的第一点和第二点，第一点和第二点沿着第一线性方向布置。沟槽段包括沿与第一方向不同的方向延伸的部分。

8. 发明授权

US09478639B2 Electrode-aligned selective epitaxy method for vertical power devices 有权
标题翻译：用于垂直功率器件的电极对准选择性外延法
公开(公告)号：US09478639B2
公开(公告)日：2016-10-25
申请号：US14633359
申请日：2015-02-27
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Oliver Blank , Rudolf Rothmaler , Johannes Baumgartl
IPC分类号： H01L21/00 , H01L29/66 , H01L21/02 , H01L29/49
CPC分类号： H01L29/66666 , H01L21/02238 , H01L21/02255 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L29/4916 , H01L29/66545
摘要： A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.
摘要翻译：一种形成沟槽电极结构的方法包括：在半导体衬底上形成第一介电层，在第一介电层上方形成第二层，并形成一个延伸穿过第二层和第一介质层到半导体衬底的开口，未覆盖半导体衬底。该方法还包括在半导体衬底的未覆盖部分上形成外延层，在形成外延层之后去除第二层，并用导电材料填充通过去除第二层形成的开放空间。导电材料形成由外延层横向包围的电极。

9. 发明申请

US20160149028A1 SEMICONDUCTOR DEVICE WITH CHARGE COMPENSATION REGION UNDERNEATH GATE TRENCH 有权
标题翻译：具有充电补偿区域的下半导体器件
公开(公告)号：US20160149028A1
公开(公告)日：2016-05-26
申请号：US14554193
申请日：2014-11-26
申请人： Infineon Technologies Austria AG
发明人： Minghao Jin , Li Juin Yip , Oliver Blank , Martin Vielemeyer , Franz Hirler
IPC分类号： H01L29/78 , H01L29/40 , H01L21/266 , H01L21/306 , H01L21/308 , H01L29/06 , H01L29/66
CPC分类号： H01L29/063 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/401 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.
摘要翻译：半导体衬底具有与主表面垂直间隔开的主表面和后表面，第一掺杂区，第二掺杂区和第三掺杂区。第三掺杂区域介于主表面下方的第一和第二掺杂区域之间。具有场板的场板沟槽从主表面垂直延伸到布置在第一掺杂区域中的底部。具有栅电极的栅极沟槽从主表面垂直延伸到第一掺杂区域。补偿区域从栅极沟槽的底部垂直地延伸到第一掺杂区域。补偿区域与栅极沟槽横向对齐，并且沿着平行于主表面的器件的横截面平面邻近场板。

10. 发明授权

US09324823B2 Semiconductor device having a tapered gate structure and method 有权
标题翻译：具有锥形栅极结构和方法的半导体器件
公开(公告)号：US09324823B2
公开(公告)日：2016-04-26
申请号：US14460716
申请日：2014-08-15
申请人： Infineon Technologies Austria AG
发明人： Oliver Blank , Rudolf Rothmaler , Christof Altstaetter , Minghao Jin
IPC分类号： H01L21/336 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/308 , H01L21/8234 , H01L29/40
CPC分类号： H01L29/42364 , H01L21/3083 , H01L21/823487 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66484 , H01L29/6656 , H01L29/66666 , H01L29/66734 , H01L29/7397 , H01L29/7813 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends into the semiconductor body from the first surface and includes first and second sidewalls extending across the semiconductor body in a lateral direction that is parallel to the first surface. A field electrode is arranged in first trench and electrically insulated from the semiconductor body by a field dielectric. A first gate electrode is arranged in the first trench. The first gate electrode is electrically insulated from the field electrode by the field dielectric and is electrically insulated from the semiconductor body by a first gate oxide. The first gate electrode includes widened and tapered portions that are continuously connected and adjacent to one another in the lateral direction. The first gate oxide forms a non-perpendicular angle with the first sidewall in the lateral direction.
摘要翻译：半导体器件包括具有与第二表面垂直间隔开的第一表面的半导体本体。第一沟槽从第一表面垂直延伸到半导体本体中，并且包括在与第一表面平行的横向方向上延伸穿过半导体本体的第一和第二侧壁。场电极布置在第一沟槽中并且通过场电介质与半导体本体电绝缘。第一栅极布置在第一沟槽中。第一栅电极通过场电介质与场电极电绝缘，并且通过第一栅极氧化物与半导体本体电绝缘。第一栅电极包括在横向方向上彼此连续连接和相邻的加宽和锥形部分。第一栅极氧化物在横向方向上与第一侧壁形成非垂直的角度。

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