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    • 2. 发明申请
    • Semiconductor memory element arrangement
    • 半导体存储元件布置
    • US20040252576A1
    • 2004-12-16
    • US10805670
    • 2004-03-19
    • Infineon Technologies AG
    • Franz HofmannRichard Johannes LuykenMichael Specht
    • G11C008/02
    • H01L27/11517H01L27/115
    • Method for fabricating a semiconductor memory element arrangement. A layer system, including a floating gate and a tunnel barrier arrangement formed on the floating gate, is formed on an electrically insulating layer. A first trench structure is formed in the layer system, and the first trench structure has first parallel trenches extending as far as the insulating layer. A second trench structure is formed in the layer system, and has second parallel trenches arranged perpendicular to the first trenches and extending as far as the insulating layer. First and second gate electrodes are formed in the first and second trench structures. The first gate electrode is adjacent to the floating gate through which first gate electrode electrical charge can be fed or can be dissipated from. The second gate electrode is adjacent to the tunnel barrier arrangement, and can control an electrical charge transmission of the tunnel barrier arrangement.
    • 半导体存储元件布置的制造方法。 在电绝缘层上形成包括形成在浮动栅极上的浮动栅极和隧道势垒装置的层系统。 在层系统中形成第一沟槽结构,并且第一沟槽结构具有延伸至绝缘层的第一平行沟槽。 在层系统中形成第二沟槽结构,并且具有垂直于第一沟槽布置并延伸至绝缘层的第二平行沟槽。 第一和第二栅电极形成在第一和第二沟槽结构中。 第一栅电极与浮置栅极相邻,第一栅电极电荷可以通过该栅极馈送或可从其中消散。 第二栅电极与隧道势垒装置相邻,并且可以控制隧道势垒装置的电荷传输。
    • 7. 发明申请
    • Memory cell
    • 存储单元
    • US20040183125A1
    • 2004-09-23
    • US10779557
    • 2004-02-06
    • Infineon Technologies AG
    • Franz HofmannJosef Willer
    • H01L029/788
    • H01L29/7923
    • A memory cell having a source region, a drain region, a source-end control gate, a drain-end control gate, an injection gate arranged between the source-end control gate and the drain-end control gate, a source-end storage element arranged in the source-end control gate, and a drain-end storage element arranged in the drain-end control gate. To program the memory cell, a low electrical voltage is applied to the injection gate, and a high electrical voltage is applied to the control gates.
    • 具有源极区域,漏极区域,源极端子控制栅极,漏极端子控制栅极,配置在源极端子控制栅极和漏极端子控制栅极之间的注入栅极的存储单元,源极端子存储器 排列在源极端控制栅极中的漏极端存储元件,以及布置在漏极端控制栅极中的漏极端存储元件。 为了对存储单元进行编程,将低电压施加到注入栅极,并且高电压被施加到控制栅极。