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    • 2. 发明授权
    • Method for encoding a digital communication channel
    • 数字通信信道编码方法
    • US06170077A
    • 2001-01-02
    • US09135680
    • 1998-08-18
    • In Gi LimSeong Bong LeeKwang Il YeonKyung Soo Kim
    • In Gi LimSeong Bong LeeKwang Il YeonKyung Soo Kim
    • H03M1303
    • H03M13/235H03M13/27
    • A method for encoding a digital communication channel is disclosed. The method includes the steps of first storing a frame data, which is inputted for a channel encoding operation, into an encoder RAM (ERAM0); second addressing the ERAM and storing the data into a register via a multiplexer in accordance with a control of a frame selection signal; third addressing the ERAM for reading the previous input data and storing the read data into the register; fourth selecting an input data among two register output data, inputting the selected input data into the convolutional encoder and generating a code symbol; and fifth selecting one among the code symbols and obtaining an output of the channel encoder that completed the convolutional encoding and interleaving operations.
    • 公开了一种用于对数字通信信道进行编码的方法。 该方法包括以下步骤:将针对频道编码操作输入的帧数据首先存储到编码器RAM(ERAM0)中; 第二寻址ERAM并根据帧选择信号的控制经由多路复用器将数据存储到寄存器中; 第三个寻址ERAM读取以前的输入数据并将读取的数据存储到寄存器中; 在两个寄存器输出数据之间选择一个输入数据,将选择的输入数据输入到卷积编码器并产生代码符号; 并且在代码符号中选择一个,并获得完成卷积编码和交织操作的信道编码器的输出。
    • 3. 发明授权
    • Synchronizing circuit
    • 同步电路
    • US5974102A
    • 1999-10-26
    • US929692
    • 1997-09-15
    • Ik Soo EoKwang Il YeonIn Gi Lim
    • Ik Soo EoKwang Il YeonIn Gi Lim
    • H03K19/003G06F5/06H04L7/00H04L7/02
    • H04L7/02G06F5/06H04L7/0008
    • In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.
    • 在单片机和数字信号处理块在一个芯片中一起使用的情况下,存在当从一个块向另一个块发送信号时时钟的同步彼此不一致的问题。 另外,当在输入信号变化期间激活参考时钟时,发生了不完整的间隔。 因此,为了解决上述问题,本发明公开了一种使用由NAND门构成的锁存电路(“RS”)同步异步输入数据和参考时钟的同步电路,由此解决了 不完整间隔发生。