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1. 发明授权

US07839148B2 Method and system for calibrating downhole tools for drift 有权
标题翻译：用于校准井下工具进行漂移的方法和系统
公开(公告)号：US07839148B2
公开(公告)日：2010-11-23
申请号：US11396494
申请日：2006-04-03
申请人： Imran Vehra , James J. Freeman , Christopher A. Golla , Randal T. Beste , Michael S. Bittar
发明人： Imran Vehra , James J. Freeman , Christopher A. Golla , Randal T. Beste , Michael S. Bittar
IPC分类号： G01V3/00
CPC分类号： G01V3/30 , G01V13/00
摘要： A method and related system calibrating downhole tools for drift. Some of the illustrative embodiments are a logging tool comprising a tool body, a transmitter antenna associated with the tool body, a transmitter electronics coupled to the transmitter antenna, a first receiver antenna associated with the tool body, a first receiver electronics coupled to the first receiver antenna, and a signal generator separate from the first transmitter electronics, the signal generator coupled to the first receiver electronics, and the first signal generator provides a calibration signal to the first receiver electronics.
摘要翻译：一种校准井下工具进行漂移的方法和相关系统。示例性实施例中的一些是测井工具，其包括工具主体，与工具主体相关联的发射器天线，耦合到发射器天线的发射器电子器件，与工具主体相关联的第一接收器天线，耦合到第一接收器天线和与第一发射机电子装置分离的信号发生器，信号发生器耦合到第一接收器电子装置，第一信号发生器向第一接收器电子装置提供校准信号。

2. 发明授权

US07307425B2 Receiver electronics proximate antenna 有权
标题翻译：靠近天线的接收机电子设备
公开(公告)号：US07307425B2
公开(公告)日：2007-12-11
申请号：US10992129
申请日：2004-11-18
申请人： James J. Freeman , Imran Vehra , Christopher A. Golla , Sergei Sharonov
发明人： James J. Freeman , Imran Vehra , Christopher A. Golla , Sergei Sharonov
IPC分类号： G01V3/30
CPC分类号： E21B47/0002 , B81B2207/115 , E21B47/011 , G01V1/40 , H01L21/86 , H01L23/3157 , H01L27/12 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： A resistivity tool includes receiver electronics near each receiver antenna loop. Placement of the electronics in this position such as at the circuit card between the terminal ends of the receiver antenna loop improves signal to noise ratio by reducing or eliminating interference, noise, and cross-talk of transmissions from the receiver to a remote microprocessor. By using material such as silicon-on-sapphire, electronics can be miniaturized and operate reliably at when exposed to high temperatures, even for long periods.
摘要翻译：电阻率工具包括靠近每个接收机天线环路的接收机电子设备。在接收器天线环路的终端之间的诸如电路卡之间的电子设备的放置通过减少或消除从接收器到远程微处理器的传输的干扰，噪声和串扰来提高信噪比。通过使用诸如蓝宝石之类的材料，即使长时间暴露在高温下，电子器件也可以小型化并可靠地运行。

3. 发明授权

US07301223B2 High temperature electronic devices 有权
标题翻译：高温电子设备
公开(公告)号：US07301223B2
公开(公告)日：2007-11-27
申请号：US10992145
申请日：2004-11-18
申请人： Paul F. Rodney , James E. Masino , Christopher A. Golla , Roger L. Schultz , James J. Freeman
发明人： Paul F. Rodney , James E. Masino , Christopher A. Golla , Roger L. Schultz , James J. Freeman
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： E21B47/0002 , B81B2207/115 , E21B47/011 , G01V1/40 , H01L21/86 , H01L23/3157 , H01L27/12 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.
摘要翻译：在至少一些实施例中，适于在超过200℃的温度下使用的电子器件可以包括在碳化硅衬底上制造的集成电路和厚钝化层。在其它实施例中，适于在超过200℃的温度下使用的电子器件可以包括由位于蓝宝石衬底上的硅形成的集成电路和厚钝化层。电子设备可以在碳氢化合物钻井和生产操作的背景下实现。

4. 发明申请

US20120086460A1 SYSTEM AND METHOD FOR OPERATING MONITORING ELEMENTS AND SINGLE USE ELEMENTS WITH A COMMON CABLE 审中-公开
标题翻译：使用通用电缆操作监控元件和单个使用元件的系统和方法
公开(公告)号：US20120086460A1
公开(公告)日：2012-04-12
申请号：US12902323
申请日：2010-10-12
申请人： James J. Freeman
发明人： James J. Freeman
IPC分类号： G01R31/02
CPC分类号： E21B47/00
摘要： A system includes a common line configured to conduct electrical power and one or more monitoring devices coupled to the common line and configured to operate when a positive voltage is provided on the common line. The system also includes a single use device coupled to the common line and an activation circuit coupled between the single use device and the common line, the activation circuit only allowing current to flow through the single use device when a negative voltage is provided on the common line.
摘要翻译：系统包括配置为传导电力的公共线路和耦合到公共线路的一个或多个监控设备，并且被配置为当在公共线路上提供正电压时操作。该系统还包括耦合到公共线路的单次使用装置和耦合在单次使用装置和公共线路之间的激活电路，激活电路仅在公共电源上提供负电压时允许电流流过单个使用装置线。

5. 发明授权

US07442932B2 High temperature imaging device 有权
标题翻译：高温成像装置
公开(公告)号：US07442932B2
公开(公告)日：2008-10-28
申请号：US10992557
申请日：2004-11-18
申请人： Roger L. Schultz , James J. Freeman , Neal G. Skinner , Steven G. Streich
发明人： Roger L. Schultz , James J. Freeman , Neal G. Skinner , Steven G. Streich
IPC分类号： G01J5/00
CPC分类号： G11C11/22 , H01L21/84 , H01L27/11502 , H01L27/12 , H01L27/1203 , H01L27/14601 , H01L27/14625
摘要： High temperature imaging devices are disclosed. In one embodiment, the imaging device comprises an array of photosensitive elements fabricated on an insulator substrate, and an information storage component coupled to the array. The information storage component stores data representing one or more light patterns detected by the array. The light patterns may be images or spectral patterns. The insulator substrate may be a sapphire or spinel substrate. Alternatively, the substrate may be silicon carbide or an insulated silicon substrate. In at least some embodiments, a processor is integrated on the same substrate as the array.
摘要翻译：公开了高温成像装置。在一个实施例中，成像装置包括制造在绝缘体衬底上的感光元件的阵列和耦合到阵列的信息存储部件。信息存储部件存储表示由阵列检测出的一个或多个光模式的数据。光图案可以是图像或光谱图案。绝缘体衬底可以是蓝宝石或尖晶石衬底。或者，衬底可以是碳化硅或绝缘硅衬底。在至少一些实施例中，处理器集成在与阵列相同的衬底上。

6. 发明授权

US06972556B2 System and method for measuring the power consumed by a circuit on a printed circuit board 有权
标题翻译：用于测量印刷电路板上的电路消耗的功率的系统和方法
公开(公告)号：US06972556B2
公开(公告)日：2005-12-06
申请号：US10894240
申请日：2004-07-20
申请人： James M. Kronrod , James J. Freeman , Kelly Coffey
发明人： James M. Kronrod , James J. Freeman , Kelly Coffey
IPC分类号： G01R1/20 , G01R19/165 , H05K1/02 , G01R11/32 , G01R7/00
CPC分类号： G01R19/16571 , G01R1/203 , H05K1/0268 , H05K2201/093 , H05K2201/09627
摘要： A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.
摘要翻译：一种用于测量包括第一和第二电路，电源板，电源平面和校准条的印刷电路板（PCB）上的电路的功率的系统。电源板连接到第一电路的电源平面，在制造过程中嵌入在PCB中，并且还具有至少两个用于测量电压降的通孔。校准条在制造过程中也嵌入到PCB中，并且具有至少两个用于测量电压降的通孔。第二电路被配置为测量作为第一电压的电源板上的电压降和跨越校准条的电压降作为第二电压，并且基于第一电压和第二电压来计算馈送到第一电路的功率电压。

7. 发明授权

US08857507B2 Downhole communication system and method 有权
标题翻译：井下通信系统及方法
公开(公告)号：US08857507B2
公开(公告)日：2014-10-14
申请号：US11972036
申请日：2008-01-10
申请人： James J. Freeman
发明人： James J. Freeman
IPC分类号： E21B47/12 , G01V11/00
CPC分类号： E21B47/12 , G01V11/002
摘要： A downhole communication system including a plurality of addressed downhole devices, a plurality of remote devices, and a plurality of conductors. Each of the plurality of conductors is electrically conductively connected to at least one of the plurality of addressed downhole devices and at least one of the plurality of remote devices. The downhole communication system is configured such that at least one of the plurality of devices is able to receive and recognize encoded addresses and encoded data in an electrical signal transmitted to at least one of the plurality of conductors electrically conductively isolated from the device configured to be receptive to the electrical signal having the encoded addresses and encoded data.
摘要翻译：一种井下通信系统，包括多个寻址井下装置，多个远程装置和多个导体。多个导体中的每一个导电地连接到多个寻址井下装置中的至少一个以及多个远程装置中的至少一个。所述井下通信系统被配置为使得所述多个设备中的至少一个能够接收并识别被传送到所述多个导体中的至少一个的编码地址和编码数据，所述至少一个导体与被配置为接收具有编码地址和编码数据的电信号。

8. 发明授权

US06861834B2 System and method for measuring the power consumed by a circuit on a printed circuit board 有权
公开(公告)号：US06861834B2
公开(公告)日：2005-03-01
申请号：US09892850
申请日：2001-06-28
申请人： James M. Kronrod , James J. Freeman , Kelly Coffey
发明人： James M. Kronrod , James J. Freeman , Kelly Coffey
IPC分类号： G01R1/20 , G01R19/165 , H05K1/02 , G01R27/28
CPC分类号： G01R19/16571 , G01R1/203 , H05K1/0268 , H05K2201/093 , H05K2201/09627
摘要： A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.

9. 发明授权

US4364078A Edge barrier of polysilicon and metal for integrated circuit chips 失效
标题翻译：用于集成电路芯片的多晶硅和金属的边缘势垒
公开(公告)号：US4364078A
公开(公告)日：1982-12-14
申请号：US150439
申请日：1980-05-16
申请人： Paul W. Smith , James J. Freeman , Donald D. Forsythe , Megha Shyam , Kenneth K. Yagura , Gunnar Wetlesen
发明人： Paul W. Smith , James J. Freeman , Donald D. Forsythe , Megha Shyam , Kenneth K. Yagura , Gunnar Wetlesen
IPC分类号： H01L21/304 , H01L23/58 , H01L29/34
CPC分类号： H01L23/585 , H01L21/3043 , H01L2924/0002
摘要： An aluminum over silicon barrier extends over the lateral edges of an integrated circuit chip into adjacent scribe lines forming an edge barrier.
摘要翻译：硅上的铝屏障在集成电路芯片的横向边缘上延伸到形成边缘屏障的相邻划线中。

10. 发明申请

US20090251960A1 HIGH TEMPERATURE MEMORY DEVICE 审中-公开
标题翻译：高温存储器件
公开(公告)号：US20090251960A1
公开(公告)日：2009-10-08
申请号：US12098549
申请日：2008-04-07
申请人： Roger L. Schultz , James J. Freeman
发明人： Roger L. Schultz , James J. Freeman
IPC分类号： H01L29/12 , G11C16/04 , G11C11/02 , G11C11/22
CPC分类号： G11C5/04 , G11C8/10 , G11C11/161 , G11C11/1675 , G11C11/22 , G11C16/0416 , H01L27/1159 , H01L27/222 , H01L29/7881
摘要： Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.
摘要翻译：本文公开了适用于在高温下使用的各种非易失性集成器件实施例。在一些实施例中，高温非易失性集成器件包括具有设置在其上的多个铁电存储器单元的蓝宝石或尖晶石衬底。在其他实施例中，高温非易失性集成器件包括绝缘体上硅衬底或具有设置在其上的多个铁电或磁存储单元的大带隙半导体衬底。在其他实施例中，高温非易失性集成器件包括蓝宝石，绝缘体上硅或具有可编程只读存储器（PROM）单元或设置在其上的电可擦除PROM（EEPROM）单元）的大带隙衬底。

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